TSPC106AMGS66CG E2V, TSPC106AMGS66CG Datasheet - Page 32

• Manufacturer Part Number: TSPC106AMGS66CG
• Manufacturer: E2V

Specifications of TSPC106AMGS66CG

• Operating Temperature Classification: Military
• Operating Temperature (max): 125C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

When more than one 60x processor is used, nine signals of the L2 interface change
their functions (to BR[1:3], BG[1:3] and DBG[1:3]) to allow for arbitration between the
60x processors. The 60x processors share all 60x interface signals of the TSPC106,
except the bus request (BR), bus grant (BG) and the data bus grant (DBG) signals.
When an external L2 controller (or integrated L2 cache module) is used, three signals of
the L2 interface change their functions (to BRL2, BGL2 and DBGL2) to allow the
TSPC106 to arbitrate between the external cache and the 60x processor(s).
Memory Interface
The memory interface controls processor and PCI interactions to main memory. It is
capable of supporting a variety of DRAM or extended data out (EDO) DRAM and ROM
or Flash ROM configurations as main memory. The maximum supported memory size is
1-Gbyte of DRAM or EDO DRAM, with 16M bytes of ROM or Flash ROM. The memory
controller of the TSPC106 supports the various memory sizes through software initial-
ization of on-chip configuration registers. Parity or ECC is provided for error detection.
The TSPC106 controls the 64-bit data path to main memory (72-bit data path with parity
or ECC). To reduce loading on the data bus, system designers must implement buffers
between the 60x bus and memory. The TSPC106 features configurable data/parity
buffer control logic to accommodate several buffer types.
The TSPC106 is capable of supporting a variety of DRAM/EDO configurations.
DRAM/EDO banks can be built of SIMMS, DIMMs or directly-attached memory devices.
Thirteen multiplexed address signals provide for device densities up to 16 Mbits. Eight
row address strobe (RAS[0:7]) signals support up to eight banks of memory. The
TSPC106 supports bank sizes from 2M bytes to 128M bytes. Eight column address
strobe (CAS[0:7]) signals are used to provided byte selection for memory bank access
(note that all CAS signals are driven in ECC mode).
The TSPC106 provides parity checking and generation in two forms, normal parity and
read-modify-write (RMW) parity. As an alternative to simple parity, the TSPC106tspc106
supports error checking and correction (ECC) for system memory. Using ECC, the
TSPC106 detects and corrects all single-bit errors and detects all double-bit errors and
all errors within a nibble (i.e., four bits or one-half byte).
For ROM/Flash support, the TSPC106 provides 20 address bits (21 address bits for the
8-bit wide ROM interface), two bank selects, one output enable, and one Flash ROM
write enable. The 16-Mbyte ROM space is subdivided into two 8-Mbyte banks. Bank 0
(selected by RCS0) is addressed from 0xFF80_0000 to 0xFFFF_FFFF. Bank 1
(selected by RCS1) is addressed from 0xFF00_0000 to 0xFF7F_FFFF. A configuration
signal, flash output enable (FOE) sampled at reset, determines the bus width of the
ROM or Flash device (8-bit or 64-bit) in bank 0. The data bus width for ROM bank 1 is
always 64 bits. For systems using the 8-bit interface to bank 0, the ROM/Flash device
must be connected to the most-significant byte lane of the data bus (DH[0:7]).
The TSPC106 also supports a mixed ROM system configuration. That is, the system
can have the upper 8M bytes (bank 0) of ROM space located on the PCI bus and the
lower 8M bytes (bank 1) of ROM located on the 60x/memory bus.
TSPC106A
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2102C–HIREL–01/05