TSPC106AMGS66CG E2V, TSPC106AMGS66CG Datasheet - Page 26

• Manufacturer Part Number: TSPC106AMGS66CG
• Manufacturer: E2V

Specifications of TSPC106AMGS66CG

• Operating Temperature Classification: Military
• Operating Temperature (max): 125C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

Input AC Specifications
Table 17. Input AC Timing Specifications (V
Notes:
26
Ref
10a
10a
10a
10a
10b
10b
11a
11b
10c
11c
1. Input specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the 1.4V of the rising edge of
2. Processor and memory interface signals are specified from the rising edge of the 60x bus clock.
3. Group I input signals include the following processor, L2 and memory interface signals: A[0:31], PAR[0:7]/AR[1:8],BR[0:4],
4. Group II input signals include the following processor and memory interface signals: TBST, TT[0:4], TSIZ[0:2], WT, CI, GBL,
5. Group III input signals include the following processor and memory interface signals: DL[0:31] and DH[0:31].
6. Group IV input signals include the following processor and L2 interface signals: TS, ARTRY, DIRTY_IN and HIT (when con-
7. PCI 3.3 V signaling environment signals are measured from 1.65V (V
8. Group V input signals include the following bussed PCI interface signals: FRAME, C/BE[0:3], AD[0:31], DEVSEL, IRDY,
9. Group VI input signal is the point-to-point PCI GNT input signal.
10. The setup and hold time is with respect to the rising edge of HRST. Mode select inputs include the RCS0, FOE and DBG0
11. t
12. These values are guaranteed by design and are not tested.
Characteristic
Group I input signals valid to SYSCLK (input
setup)
Group II input signals valid to SYSCLK (input
setup)
Group III input signals valid to SYSCLK (input
setup)
Group IV input signals valid to SYSCLK (input
setup)
Group V input signals valid to SYSCLK (input
setup)
Group VI input signals valid to SYSCLK (input
setup)
60x Bus Clock to group I - IV inputs invalid (input
hold)
SYSCLK to group V - VI inputs invalid (input hold)
9)
HRST pulse width
Mode select inputs valid to HRST (input setup)
11, 12)
HRST to mode select input invalid (input hold)
TSPC106A
the input SYSCLK. Input and output timings are measured at the pin.
BRL2, XATS, LBCLAIM, ADS, BA0, TV and HIT (when configured for external L2).
AACK and TA.
figured for internal L2 controller).
V
PCI 5V signaling environment signals are measured from 1.65V (V
= 0.55V.
TRDY, STOP, PAR, PERR, SERR, LOCK, FLSHREQ, and ISA_MASTER.
configuration inputs.
given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the
parameter in question.
SYSCLK
OL
(3, 4, 5, 6)
= 0.3V.
(1, 2, 3)
(1, 2, 4)
(1, 2, 5)
(1, 2, 6)
(7, 8)
(7, 9)
is the period of the external clock (SYSCLK) in nanoseconds (ns). When the unit is given as t
Table 17 provides the input AC timing specifications as shown in Figure 8 and Figure 9.
DD
= 3.3V ± 5% dc, GND = 0V dc, C
(10, 12)
(10,
(8,
255 x t
3 x t
+100 µs
Min
-0.5
4.0
3.5
3.0
5.0
7.0
7.0
1.0
SYSCLK
0
SYSCLK
66 MHz
DD
÷ 2) on the rising edge of SYSCLK to V
DD
÷ 2) on the rising edge of SYSCLK to V
Max
L
= 50 pF, -55°C ≤ T
255 x t
3 x t
+100 µs
Min
-0.5
3.5
3.5
2.5
4.0
7.0
7.0
1.0
SYSCLK
0
SYSCLK
83.3 MHz
j
≤ 125°C)
SYSCLK
Max
2102C–HIREL–01/05
OH
= 2.4V or V
the numbers
OH
= 3.0V or
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OL