TSPC106AMGS66CG E2V, TSPC106AMGS66CG Datasheet - Page 16

• Manufacturer Part Number: TSPC106AMGS66CG
• Manufacturer: E2V

Specifications of TSPC106AMGS66CG

• Operating Temperature Classification: Military
• Operating Temperature (max): 125C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

PCI Interface Signals
Table 7. PCI Interface Signals
16
Signal
AD[31:0]
C/BE[3:0]
DEVSEL
FLSHREQ
FRAME
GNT
IRDY
ISA_
MASTER
LOCK
MEMACK
TSPC106A
Signal Name
Address/data
Command/byte
enable
Device select
Flush request
Frame
PCI bus grant
Initializer ready
ISA master
Lock
Memory
acknowledge
Table 7 lists the PCI interface signals and provides a brief description of their functions.
Note that the bits in Table 7 are referenced in little-endian format.
The PCI specification defines a sideband signal as any signal, not part of the PCI speci-
fication, that connects two or more PCI-compliant agent, and has meaning only to those
agents. The TSPC106 implements four PCI sideband signals -FLSHREQ,
ISA_MASTER, MEMACK and PIRQ.
Number of
Pins
32
4
1
1
1
1
1
1
1
1
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
Indicates that an ISA master is requesting system memory.
Signal Description
Represents the physical address during the address phase of a
transaction. During the data phase(s) of a PCI transaction, AD[31:0]
contain data. AD[7:0] define the least significant byte and AD[31:24]
the most significant byte.
During the address phase, C/BE[3:0] define the PCI bus command.
During the data phase, C/BE[3:0] are used as byte enables. Byte
enables determine which byte lanes carry meaningful data. C/BE0
applies to the least significant byte.
During the address phase, C/BE[3:0] indicates the PCI bus command
that another master is sending. During the data phase C/BE[3:0]
indicate which byte lanes are valid.
Indicates that the TSPC106 has decoded the address and is the target
of the current access.
Indicates that some PCI agent (other than the TSPC106) has decoded
its address as the target of the current access.
Indicates that a device needs to have the TSPC106 flush all of its
current operations.
Indicates that the TSPC106, acting as a PCI master, is initiating a bus
transaction.
Indicates that another PCI master is initiating a bus transaction.
Indicates that the TSPC106 has been granted control of the PCI bus.
Note that GNT is a point-to-point signal. Every master has its own GNT
SIGNAL.
current data phase of a PCI transaction. During a write, the TSPC106
asserts IRDY to indicate that valid data is present on AD[31:0]. During
a read, the TSPC106 asserts IRDY to indicate that it is prepared to
accept data.
Indicates another PCI master is able to complete the current data
phase of the transaction.
Indicates that a master is requesting exclusive access to memory,
which may require multiple transactions to complete.
Indicates that the TSPC106 has flushed all of its current operations
and has blocked all 60x transfers except snoop copy-back operations.
The TSPC106 asserts MEMACK in response to assertion of
FLSHREQ after the flush is complete.
Indicates that the TSPC106, acting as a PCI master, can complete the
2102C–HIREL–01/05