ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 166
ML610Q409-NNNTBZ03A7
Manufacturer Part Number
ML610Q409-NNNTBZ03A7
Description
MCU 8BIT 16K FLASH 4CH 100-TQFP
Manufacturer
Rohm Semiconductor
Series
-r
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q407P-NNNTB03A7.pdf
(33 pages)
3.ML610Q407P-NNNTB03A7.pdf
(391 pages)
Specifications of ML610Q409-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
2MHz
Connectivity
SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.25 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q409-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q407P-NNNTB03A7 PDF datasheet #2
- ML610Q407P-NNNTB03A7 PDF datasheet #3
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- Download datasheet (2Mb)
11.2.2 Watchdog Timer Control Register (WDTCON)
Address: 0F00EH
Access: W
Access size: 8-bit
Initial value: 00H
WDTCON is a special function register (SFR) to clear the WDT counter.
When WDTCON is read, the value of the internal pointer (WDP) is read from bit 0.
[Description of Bits]
Note:
When the WDT interrupt (WDTINT) occurs by the first WDT counter overflow, the counter and the internal pointer
(WDP) are initialiaed for a half cycle of low speed clock (about 15us). During the time period that they are initialized,
writing to WDTCON is disable and the logic of WDP does not change. Therefore, in the case of that you have
program codes handle to clear the WDT when the first overflow WDT interrupt occurs and also the codes run at
high-speed system clock, please check the WDP gets reversed after writing to WDTCON to see if the writing was
surely successful. For example of the program code, see Section 11.3.1, "Handling example when you do not want to
use the watch dog timer".
Initial value
WDTCON
• WDP/d0 (bit 0)
• d7-d0 (bits 7-0)
R/W
The value of the internal pointer (WDP) is read from this bit. The WDP is reset to “0” at the system reset or WDT
counter overflow and is inverted every writing to WDTCON.
This bit is used to write data to clear the WDT counter. The WDT counter can be cleared by writing "5AH" with
the internal pointer (WDP) is "0", then writing "0A5H" with the WDP "1".
R/W
d7
7
0
R/W
d6
6
0
R/W
d5
5
0
11-3
R/W
d4
4
0
ML610Q407/ML610Q408/ML610Q409 User's Manual
R/W
d3
3
0
R/W
d2
2
0
Chapter 11 Watchdog Timer
R/W
d1
0
1
WDP/d0
R/W
0
0
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