ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 214

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ML610Q409-NNNTBZ03A7

Manufacturer Part Number
ML610Q409-NNNTBZ03A7
Description
MCU 8BIT 16K FLASH 4CH 100-TQFP
Manufacturer
Rohm Semiconductor
Series
-r

Specifications of ML610Q409-NNNTBZ03A7

Core Processor
nX-U8/100
Core Size
8-Bit
Speed
2MHz
Connectivity
SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.25 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ML610Q409-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 13 UART
13.4 Specifying port registers
13.4.1 Functioning P43(TXD0) and P42(RXD0) as the UART
and Chapter 18, “Port 0” for detail about the port registers.
the value "1" selects the P43.
To enable the UART function, the applicable bit of each related port register needs to be set. See Chapter 21, “Port 4”
Set P43MD1-P42MD1 bits(bit3-bit2 of P4MOD1 register) to “0” and set P43MD0-P42MD0(bit3-bit2 of P4MOD0
register) to “1”, for specifying the UART as the secondary function of P43 and P42.
Set the P43C1 bit (P4CON1 register's bit 3) to "1", the P43C0 bit (P4CON0 register's bit 3) to "1", and the P43DIR bit
(P4DIR register's bit 3) to "0" for specifying the state mode of the P43 pin to CMOS output.
Set P42DIR bit (bit2 of P4DIR register) to “1” for specifying the P42 as an input pin.
The set value ($) is arbitrary for the P42C1 and P42C0 bits. Select an arbitrary input mode depending on the state of the
external circuit to which the P42 pin is connected.
The P43D to D42D bits (P4D register bits 3 to 2) data can either be "0" or "1" (not need to be set).
* : Bit not related to the UART function
** : Don’t care
[Note:]
The receive pin (RXD) is selected by U0RSEL bit (bit4 of UA0MOD0 register). The initial value "0" selects the P02 and
Register name
Register name
Register name
Register name
Register name
Register name
Setting value
Setting value
Setting value
Setting value
Setting value
Setting value
Bit name
Bit name
Bit name
Bit name
Bit name
Bit name
Bit
Bit
Bit
Bit
Bit
Bit
P47MD1
P47MD0
P47DIR
P47C1
P47C0
P47D
7
7
7
7
7
7
*
*
*
*
*
*
P46MD1
P46MD0
P46DIR
P46C1
P46C0
P46D
6
6
6
6
6
6
*
*
*
*
*
*
$: Optional
P45MD1
P45MD0
P45DIR
P45C1
P45C0
P45D
P4MOD1 register (Address: 0F225H)
P4MOD0 register (Address: 0F224H)
5
5
P4CON1 register (Address: 0F223H)
5
P4CON0 register (Address: 0F222H)
5
5
5
*
*
*
*
*
*
P4DIR register (Address: 0F221H)
P4D register (Address: 0F220H)
13-20
P44MD1
P44MD0
P44DIR
P44C1
P44C0
P44D
4
4
4
4
4
4
*
*
*
*
*
*
P43MD1
P43MD0
P43DIR
P43C1
P43C0
P43D
**
3
0
3
1
3
1
3
1
3
0
3
P42MD1
P42MD0
P42DIR
P42C1
P42C0
P42D
**
2
0
2
1
2
$
2
$
2
1
2
P41MD1
P41MD0
P41DIR
P41C1
P41C0
P41D
1
1
1
1
1
1
*
*
*
*
*
*
P40MD1
P40MD0
P40DIR
P40C1
P40C0
P40D
0
0
0
0
0
0
*
*
*
*
*
*

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