ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 344
ML610Q409-NNNTBZ03A7
Manufacturer Part Number
ML610Q409-NNNTBZ03A7
Description
MCU 8BIT 16K FLASH 4CH 100-TQFP
Manufacturer
Rohm Semiconductor
Series
-r
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q407P-NNNTB03A7.pdf
(33 pages)
3.ML610Q407P-NNNTB03A7.pdf
(391 pages)
Specifications of ML610Q409-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
2MHz
Connectivity
SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.25 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q409-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q407P-NNNTB03A7 PDF datasheet #2
- ML610Q407P-NNNTB03A7 PDF datasheet #3
- Current page: 344 of 391
- Download datasheet (2Mb)
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Unused address region and test region program for ML610402 (low speed clock stop detection reset enable
setting)
Unused address region and test region program for ML610403 (low speed clock stop detection reset enable
setting)
Filling the extra area at code memory (for ML610Q402)
Filling the Test area at code memory (for ML610Q402)
Keeping the Mirror area (for ML610Q402)
Filling the extra area at code memory (for ML610Q403)
Filling the Test area at code memory (for ML610Q403)
Keeping the Mirror area (for ML610Q403)
cseg at 01700h
dw 1280h
cseg at 03c00h
dw 0f4h
cseg at 03de8h
dw
dw
dw
dw
cseg at 03df0h
dw 8h
tseg #8 at 00000h
ds
cseg at 01700h
dw 1280h
cseg at 03c00h
dw 0f4h
cseg at 03de8h
dw
dw
dw
dw
cseg at 03df0h
dw 8h
tseg #8 at 00000h
ds
03e00h
03e00h
04020h
02948h
000f0h
0a55ah
04030h
02848h
000f0h
0a55ah
DUP 0ffffh
DUP 0ffffh
DUP 0ffffh ;
DUP 0ffffh ;
DUP 0ffffh
DUP 0ffffh
;Target configuration data 3
;Target configuration data 3
;Target configuration data 4
;Target configuration data 4
;Target configuration data 1
;Target configuration data 2
;Target configuration data 1
;Target configuration data 2
25-3
Chapter 25 Mask Type Emulation Function
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