ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 187

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 12 Synchronous Serial Port
12.4.2 Functioning P42 (SOUT0: Output), P41 (SCK0: Input/output), and P40 (SIN0: Input) as
Set the P42MD1 to P40MD1 bits (P4MOD1 register bits 2 to 0) to “1” and the P42MD0 to P40MD0 bits (P4MOD0
register bits 2 to 0) to “0” for selecting the SSIO as the tertiary function of the P42, P41 and P40. They are the same
setting as those in the case of master mode.
Set the P42C1 bit (P4CON1 register bit 2) to "1", the P42C0 bit (P4CON0 register bit 2) to "1", and the P42DIR bit
(P4DIR register bit 2) to "0" for selecting the P42 pin state mode to CMOS output.
Set P41DIR to P40DIR bits (P4DIR register bit 1 to 0) to “1” for specifying the P41 and P40 as input pins.
The set value ($) is arbitrary for the P41C1 to P40C1 bits and for the P41C0 to P40C0 bits. Select an arbitrary input
mode depending on the state of the external circuit to which the P41 or P40 pin is connected.
The data of the P42D to P40D bits (P4D register bits 2 to 0) can either be "0" or "1".
* : Bit not related to the SSIO0 function
** : Don’t care
Register name
Register name
Register name
Register name
Register name
Register name
Setting value
Setting value
Setting value
Setting value
Setting value
Setting value
the SSIO0/ ”Slave mode”
Bit name
Bit name
Bit name
Bit name
Bit name
Bit name
Bit
Bit
Bit
Bit
Bit
Bit
P47MD1
P47MD0
P47DIR
P47C1
P47C0
P47D
7
7
7
7
7
7
*
*
*
*
*
*
P46MD1
P46MD0
P46DIR
P46C1
P46C0
P46D
6
6
6
6
6
6
*
*
*
*
*
*
$: Optional
P45MD1
P45MD0
P45DIR
P45C1
P45C0
P45D
P4MOD1 register (Address: 0F225H)
P4MOD0 register (Address: 0F224H)
5
5
P4CON1 register (Address: 0F223H)
5
P4CON0 register (Address: 0F222H)
5
5
5
*
*
*
*
*
*
P4DIR register (Address: 0F221H)
P4D register (Address: 0F220H)
12-16
P44MD1
P44MD0
P44DIR
P44C1
P44C0
P44D
4
4
4
4
4
4
*
*
*
*
*
*
P43MD1
P43MD0
P43DIR
P43C1
P43C0
P43D
3
3
3
3
3
3
*
*
*
*
*
*
P42MD1
P42MD0
P42DIR
P42C1
P42C0
P42D
**
2
1
2
0
2
1
2
1
2
0
2
P41MD1
P41MD0
P41DIR
P41C1
P41C0
P41D
**
1
1
1
0
1
$
1
$
1
1
1
P40MD1
P40MD0
P40DIR
P40C1
P40C0
P40D
**
0
1
0
0
0
$
0
$
0
1
0