PCF2129AT/1,512 NXP Semiconductors, PCF2129AT/1,512 Datasheet - Page 21

• Manufacturer Part Number: PCF2129AT/1,512
• Description: IC REAL TIME CLK/CALENDAR 20SOIC
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2129AT/1,512

• Package / Case: 20-SOIC (7.5mm Width)
• Date Format: YY-MM-DD-dd
• Time Format: HH:MM:SS (12/24 hr)
• Interface: I²C, SPI
• Voltage - Supply: 1.8 V ~ 4.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Clock, Alarm, Watchdog, Timestamp
• Supply Voltage (max): 4.2 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C, SPI
• Supply Current: 800 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4960-5; 935288599512

NXP Semiconductors
PCF2129A_2
Product data sheet
8.7.1 Power-On Reset (POR)
8.7.2 Power-On Reset Override (PORO)
8.7 Reset function
The PCF2129A has a Power-On Reset (POR) and a Power-On Reset Override (PORO)
function implemented.
The POR is active whenever the oscillator is stopped. The oscillator is also considered to
be stopped during the time between power-on and stable crystal resonance (see
Figure
supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set
logic 1).
After POR, the following mode is entered:
The register values after power-on are shown in
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and therefore speed up on-board test of the device.
Fig 10. Dependency between POR and oscillator
Fig 11. Power-On Reset (POR) system
•
•
•
•
•
32.768 kHz CLKOUT active
Power-On Reset Override (PORO) available to be set
24 hour mode is selected
Battery switch-over is enabled
Battery low detection is enabled
10). This time may be in the range of 200 ms to 2 s depending on temperature and
oscillation
internal
reset
V
DD
All information provided in this document is subject to legal disclaimers.
SDA/CE
SCL
Rev. 02 — 7 May 2010
OSCILLATOR
POR_OVRD
OVERRIDE
RESET
CLEAR
chip in reset
0 = override inactive
1 = override active
0 = clear override mode
1 = override possible
0 = stopped, 1 = running
osc stopped
Integrated RTC, TCXO and quartz crystal
Table
4.
chip not in reset
001aaj324
reset
PCF2129A
© NXP B.V. 2010. All rights reserved.
001aaf897
t
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