PCF2129AT/1,512 NXP Semiconductors, PCF2129AT/1,512 Datasheet - Page 41

• Manufacturer Part Number: PCF2129AT/1,512
• Description: IC REAL TIME CLK/CALENDAR 20SOIC
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2129AT/1,512

• Package / Case: 20-SOIC (7.5mm Width)
• Date Format: YY-MM-DD-dd
• Time Format: HH:MM:SS (12/24 hr)
• Interface: I²C, SPI
• Voltage - Supply: 1.8 V ~ 4.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Clock, Alarm, Watchdog, Timestamp
• Supply Voltage (max): 4.2 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C, SPI
• Supply Current: 800 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4960-5; 935288599512

NXP Semiconductors
PCF2129A_2
Product data sheet
8.12.4 Alarm interrupts
8.12.5 Timestamp interrupts
8.12.6 Battery switch-over interrupts
8.12.7 Battery low detection interrupts
The interrupt is cleared when the flag WDTF is reset. WDTF is a read only bit and cannot
be cleared by using the interface. Instructions for clearing it can be found in
Section
Generation of interrupts from the alarm function is controlled via the bit AIE (register
Control_2). If AIE is enabled, the INT pin will follow the status of bit AF (register
Control_2). Clearing AF will immediately clear INT. No pulse generation is possible for
alarm interrupts.
Interrupt generation from the timestamp function is controlled using the TSIE bit (register
Control_2). If TSIE is enabled the INT pin follows the status of the flags TSFx. Clearing
the flags TSFx immediately clears INT. No pulse generation is possible for timestamp
interrupts.
Generation of interrupts from the battery switch-over is controlled via the BIE bit (register
Control_3). If BIE is enabled, the INT pin follows the status of bit BF in register Control_3
(see
battery switch-over interrupts.
Generation of interrupts from the battery low detection is controlled via the BLIE bit
(register Control_3). If BLIE is enabled the INT pin will follow the status of bit BLF (register
Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when
bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared via
the interface.
Fig 23. AF timing diagram
Table
8.10.5.
Example where only the minute alarm is used and no other interrupts are enabled.
44). Clearing BF immediately clears INT. No pulse generation is possible for
minute counter
All information provided in this document is subject to legal disclaimers.
minute alarm
instruction
SCL
INT
AF
Rev. 02 — 7 May 2010
44
45
45
CLEAR INSTRUCTION
Integrated RTC, TCXO and quartz crystal
8th clock
PCF2129A
001aaf910
© NXP B.V. 2010. All rights reserved.
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