PCF2129AT/1,512 NXP Semiconductors, PCF2129AT/1,512 Datasheet - Page 40

• Manufacturer Part Number: PCF2129AT/1,512
• Description: IC REAL TIME CLK/CALENDAR 20SOIC
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2129AT/1,512

• Package / Case: 20-SOIC (7.5mm Width)
• Date Format: YY-MM-DD-dd
• Time Format: HH:MM:SS (12/24 hr)
• Interface: I²C, SPI
• Voltage - Supply: 1.8 V ~ 4.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Clock, Alarm, Watchdog, Timestamp
• Supply Voltage (max): 4.2 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C, SPI
• Supply Current: 800 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4960-5; 935288599512

NXP Semiconductors
PCF2129A_2
Product data sheet
8.12.2 INT pulse shortening
8.12.3 Watchdog timer interrupts
The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock
and generates a pulse of
If the MSF flag (register Control_2) is cleared before the end of the INT pulse, then the
INT pulse is shortened. This allows the source of a system interrupt to be cleared
immediately when it is serviced, i.e. the system does not have to wait for the completion of
the pulse before continuing; see
found in
The generation of interrupts from the watchdog timer is controlled using the WD_CD bit
(register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows
the status of the watchdog timer flag WDTF (register Control_2). No pulse generation is
possible for watchdog timer interrupts.
Fig 21. INT example for SI and MI when TI_TP is logic 0
Fig 22. Example of shortening the INT pulse by clearing the MSF flag
(1) Indicates normal duration of INT pulse.
MSF when only MI enabled
Section
INT when only MI enabled
In this example, bit TI_TP is logic 0 and the MSF flag is cleared after an interrupt.
The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, i.e. when
TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic 0.
MSF when SI enable
INT when SI enable
seconds counter
All information provided in this document is subject to legal disclaimers.
seconds counter
minutes counter
8.10.5.
instruction
MSF
SCL
INT
Rev. 02 — 7 May 2010
1
⁄
64
58
seconds in duration.
58
Figure
59
59
22. Instructions for clearing the bit MSF can be
CLEAR INSTRUCTION
Integrated RTC, TCXO and quartz crystal
59
11
00
12
8th clock
00
PCF2129A
01
001aaf908
© NXP B.V. 2010. All rights reserved.
(1)
001aag072
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