PCF2129AT/1,512 NXP Semiconductors, PCF2129AT/1,512 Datasheet - Page 39

• Manufacturer Part Number: PCF2129AT/1,512
• Description: IC REAL TIME CLK/CALENDAR 20SOIC
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2129AT/1,512

• Package / Case: 20-SOIC (7.5mm Width)
• Date Format: YY-MM-DD-dd
• Time Format: HH:MM:SS (12/24 hr)
• Interface: I²C, SPI
• Voltage - Supply: 1.8 V ~ 4.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Clock, Alarm, Watchdog, Timestamp
• Supply Voltage (max): 4.2 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C, SPI
• Supply Current: 800 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4960-5; 935288599512

NXP Semiconductors
PCF2129A_2
Product data sheet
8.12.1 Minute and second interrupts
The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the
interrupts generated from the second/minute timer (flag MSF in register Control_2) are
pulsed signals or a permanently active signal. All the other interrupt sources generate a
permanently active interrupt signal which follows the status of the corresponding flags.
When the interrupt sources are all disabled, INT remains high-impedance.
Minute and second interrupts are generated by predefined timers. The timers can be
enabled independently from one another by the bits MI and SI in register Control_1.
However, a minute interrupt enabled on top of a second interrupt will not be
distinguishable since it will occur at the same time.
The minute/second flag MSF (register Control_2) is set logic 1 when either the seconds or
the minutes counter increments according to the actually enabled interrupt (see
The MSF flag can be read and cleared by the interface.
Table 45.
When MSF is set logic 1:
MI SI Result on INT
0
1
0
1
Fig 20. INT example for SI and MI when TI_TP is logic 1
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•
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•
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The flags MSF, AF, TSFx, and BF can be cleared by using the interface.
The flag WDTF is read only. How it can be cleared is explained in
The flag BLF is read only. It is cleared automatically from the battery low detection
circuit when the battery is replaced.
If TI_TP is logic 1 the interrupt is generated as a pulsed signal.
If TI_TP is logic 0 the interrupt is permanently active signal that remains until MSF is
cleared.
0
0
1
1
MSF when only MI enabled
INT when only MI enabled
MSF when SI enabled
no interrupt generated
an interrupt once per minute
an interrupt once per second
an interrupt once per second
INT when SI enabled
In this example, bit TI_TP is logic 1 and the MSF flag is not cleared after an interrupt.
Effect of bits MI and SI on pin INT and bit MSF
seconds counter
minutes counter
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 7 May 2010
58
59
Result on MSF
MSF never set
MSF set when minutes counter increments
MSF set when seconds counter increments
MSF set when seconds counter increments
Integrated RTC, TCXO and quartz crystal
59
11
00
12
PCF2129A
00
Section
© NXP B.V. 2010. All rights reserved.
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45).