PCF2129AT/1,512 NXP Semiconductors, PCF2129AT/1,512 Datasheet - Page 31

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PCF2129AT/1,512

Manufacturer Part Number
PCF2129AT/1,512
Description
IC REAL TIME CLK/CALENDAR 20SOIC
Manufacturer
NXP Semiconductors
Type
Clock/Calendar/Alarmr
Datasheets

Specifications of PCF2129AT/1,512

Package / Case
20-SOIC (7.5mm Width)
Date Format
YY-MM-DD-dd
Time Format
HH:MM:SS (12/24 hr)
Interface
I²C, SPI
Voltage - Supply
1.8 V ~ 4.2 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Function
Clock, Alarm, Watchdog, Timestamp
Supply Voltage (max)
4.2 V
Supply Voltage (min)
1.8 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Rtc Bus Interface
I2C, SPI
Supply Current
800 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4960-5
935288599512
NXP Semiconductors
PCF2129A_2
Product data sheet
8.10.3 Watchdog timer function
Table 32.
The watchdog timer function is enabled or disabled by the WD_CD bit of the register
Watchdg_tim_ctl (see
The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock
frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or
When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val
(see
The watchdog timer counts down from the software programmed 8-bit binary value n in
register Watchdg_tim_val. When the counter reaches 1 the watchdog timer flag WDTF
(register Control_2) is set logic 1 and an interrupt will be generated.
The counter does not automatically reload.
When WD_CD is logic 0 (watchdog timer disabled) and the microcontroller unit (MCU)
loads a watchdog timer value n, then:
Loading the counter with 0 will:
Remark: WDTF is read only and cannot be cleared with the interface. WDTF can be
cleared by:
Writing a logic 0 or logic 1 to WDTF has no effect.
TF[1:0] Timer source
00
01
10
11
the flag WDTF is reset
INT is cleared
the watchdog timer starts again
reset the flag WDTF
clear INT
stop the watchdog timer
loading a value in register Watchdg_tim_val
reading of the register Control_2
Table
clock frequency
4.096
64
1
1
60
Programmable watchdog timer
32) determines the watchdog timer period.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 02 — 7 May 2010
30).
Units
kHz
Hz
Hz
Hz
Minimum timer
period (n = 1)
244
15.625
1
60
Integrated RTC, TCXO and quartz crystal
Units
μs
ms
s
s
Maximum timer
period (n = 255)
62.256
3.984
255
15300
1
60
PCF2129A
Hz (see
© NXP B.V. 2010. All rights reserved.
Table
32).
Units
ms
s
s
s
31 of 69

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