AD9271BSVZRL-25 Analog Devices Inc, AD9271BSVZRL-25 Datasheet
AD9271BSVZRL-25
Specifications of AD9271BSVZRL-25
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AD9271BSVZRL-25 Summary of contents
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FEATURES 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) Input-referred noise = 1.1 nV/√ MHz typical, gain = 18 dB SPI-programmable gain = 14 dB/15.6 dB/18 dB Single-ended input; V maximum = 400 mV ...
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AD9271 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 7 Switching Specifications ...
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The AD9271 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data ...
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AD9271 SPECIFICATIONS AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 1.0 V internal ADC reference, f LPF cutoff = 1/3 × HPF cutoff = 700 kHz, full temperature, unless otherwise noted. S ...
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Parameter Conditions Harmonic Distortion Second Harmonic GAIN MHz IN at −7 dBFS Second Harmonic GAIN MHz IN at −1 dBFS Third Harmonic ...
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AD9271 1 Parameter Conditions POWER SUPPLY AVDD DRVDD CWVDD I Full-channel mode AVDD CW Doppler mode with four channels enabled I DRVDD Total Power Full-channel mode, Dissipation no signal (Including Output Drivers) CW Doppler mode with four channels enabled Power-Down ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. 1 Parameter CLOCK INPUTS (CLK+, CLK−) Logic ...
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AD9271 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. 1 Parameter 2 CLOCK Maximum Clock ...
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ADC TIMING DIAGRAMS N – 1 AIN CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO DOUTx– DOUTx+ N – 1 AIN CLK– CLK+ t CPD DCO– DCO+ t ...
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AD9271 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To ELECTRICAL AVDD GND DRVDD GND CWVDD GND GND GND AVDD DRVDD Digital Outputs GND (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− GND LI-x LG-x LO-x LG-x LOSW-x LG-x CWDx−, ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 LI-E 1 INDICATOR LG-E 2 AVDD 3 AVDD 4 LO-F 5 LOSW-F 6 LI-F 7 LG-F 8 AVDD 9 AVDD 10 LO-G 11 LOSW LI-G 13 LG-G 14 AVDD 15 AVDD ...
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AD9271 Pin No. Name 18 LOSW-H 19 LI-H 20 LG-H 23 CLK− 24 CLK+ 27 DOUTH− 28 DOUTH+ 29 DOUTG− 30 DOUTG+ 31 DOUTF− 32 DOUTF+ 33 DOUTE− 34 DOUTE+ 35 DCO− 36 DCO+ 37 FCO− 38 FCO+ 39 DOUTD− ...
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Pin No. Name 86 GAIN+ 87 RBIAS 88 SENSE 89 VREF 90 REFB 91 REFT 93 CWD3− 94 CWD3+ 95 CWD4− 96 CWD4+ 97 CWD5− 98 CWD5+ 99 LO-E 100 LOSW-E Description Gain Control Voltage Input True External Resistor to ...
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AD9271 EQUIVALENT CIRCUITS AVDD VCM 15kΩ LI-x, LG-x Figure 5. Equivalent LNA Input Circuit 10Ω LO-x, LOSW-x Figure 6. Equivalent LNA Output Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 7. Equivalent Clock Input Circuit AVDD 1.25V SCLK OR PDWN ...
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AVDD 100Ω RBIAS Figure 11. Equivalent RBIAS Circuit AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit GAIN+ Figure 15. Equivalent GAIN+ Input Circuit GAIN– Figure ...
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AD9271 TYPICAL PERFORMANCE CHARACTERISTICS MSPS MHz, LPF = 1/3 × f SAMPLE IN 2.0 1.5 1.0 0.5 +85°C 0 +25°C –40°C –0.5 –1.0 –1.5 –2.0 0 0.1 0.2 0.3 0.4 0.5 0.6 V (V) ...
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CODES Figure 24. Output-Referred Noise Histogram with V 1200000 1000000 800000 600000 400000 200000 0 –5 –4 –3 –2 –1 0 ...
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AD9271 0 –5 –3dB LINE –10 –15 (1/3) × 40MSPS –20 –25 –30 (1/3) × 25MSPS –35 –40 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY (MHz) Figure 30. Antialiasing Filter (AAF) Pass-Band Response, No HPF Applied 300 V = ...
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AIN1 = AIN2 = –7dBFS –10 –20 –30 –40 –50 8MHz AND 10.3MHz –60 –70 –80 –90 2.3MHz AND 3.5MHz –100 5MHz AND 6MHz –110 0.2 0.3 0.4 0.5 0.6 0.7 0.8 V (V) GAIN Figure 36. IMD3 vs. ...
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AD9271 THEORY OF OPERATION ULTRASOUND The primary application for the AD9271 is medical ultrasound. Figure 39 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for ...
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RFB1 CFB RFB2 T/R SWITCH CS CSH CLG CHANNEL OVERVIEW Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides user- adjustable input impedance termination. The CW Doppler ...
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AD9271 Because the amplifier has a gain of 6× from its input to its differential output important to note that the gain A/2 is the gain from Pin LI-x to Pin LO-x, and less ...
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UNTERMINATED 12 RESISTIVE TERMINATION 10 ACTIVE TERMINATION 100 R (Ω) S Figure 44. Noise Figure vs. R for Resistive Termination, Active Termination S Matched, and Unterminated Inputs, V Gain ...
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AD9271 CW DOPPLER OPERATION Modern ultrasound machines used for medical applications N employ a 2 binary array of receivers for beam forming, with typical array sizes receiver channels phase-shifted and summed together to extract coherent information. ...
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Crosspoint Switch Each LNA is followed by a transconductance amp for V/I con- version. Currents can be routed to one of six pairs of differential outputs single-ended outputs for summing. Each CWD output pin sinks 2.4 mA ...
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AD9271 0.450 LNA GAIN = 5x 0.400 0.350 LNA 0.300 GAIN = 6x 0.250 0.200 LNA GAIN = 8x 0.150 0.100 0.050 0 0 0.1 0.2 0.3 0.4 0.5 0.6 V (V) GAIN Figure 49. LNA/VGA Full-Scale Limitations Variable Gain ...
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The output-referred noise is a flat 63 nV/√Hz over most of the gain range, because it is dominated by ...
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AD9271 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9271 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins ...
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In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 59). The clock ...
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AD9271 Digital Outputs and Timing The AD9271 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard by using the SDIO pin ...
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EYE: ALL BITS 300 200 100 0 –100 –200 –300 –400 –1.5ns –1.0ns –0.5ns 0ns –200ps –100ps 0ps Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Greater ...
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AD9271 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 9. To change the output data format to twos complement, see the Memory Map section. Table ...
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When using the serial port interface (SPI), the DCO± phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO± timing, as shown in Figure ...
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AD9271 Internal Reference Operation A comparator within the AD9271 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 66), setting VREF ...
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SERIAL PORT INTERFACE (SPI) The AD9271 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization depending ...
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AD9271 This interface is flexible enough to be controlled by either serial PROMs or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the device (see the AN-812 Application Note ...
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MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index ...
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AD9271 1 Table 15. Memory Map Register Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 Chip Configuration Registers 00 chip_port_config 0 LSB first off (default) 01 chip_id 02 chip_grade X X Device Index and ...
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Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0D test_io User test mode 00 = off (default on, single alternate 10 = on, single once 11 = on, alternate once 0F flex_channel_input Filter cutoff frequency control 0000 ...
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AD9271 Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 19 user_patt1_lsb user_patt1_msb B15 B14 1B user_patt2_lsb user_patt2_msb B15 B14 21 serial_control LSB first off (default) 22 serial_ch_stat ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9271 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power ...
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AD9271 EVALUATION BOARD The AD9271 evaluation board provides all the support circuitry required to operate the AD9271 in its various modes and con- figurations. The LNA is driven differentially through a transformer. Figure 73 shows the typical bench characterization setup ...
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DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9271 Rev. B evaluation board. • Power: Connect the switching power supply that is supplied in the evaluation ...
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AD9271 QUICK START PROCEDURE The following is a list of the default and optional settings when using the AD9271 either on the evaluation board or at the system level design evaluation board is not being used, follow only ...
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SCHEMATICS AND ARTWORK Figure 75. Evaluation Board Schematic, DUT Analog Input Circuits Rev Page AD9271 06304-086 ...
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AD9271 Figure 76. Evaluation Board Schematic, DUT Analog Input Circuits (Continued) Rev Page 06304-087 ...
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AVD D U302 3 1 TRIM ADR510ART Z V- 470K 8 R30 CW D LOSW D LOSW 76 D LO- D LO- 77 CWD0- CWD0 CWD0 + CWD0 79 CWD1- CWD1 CWD1 + CWD1 ...
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AD9271 GND RSET 32 1 AVDD_3. Figure 78. Evaluation Board Schematic, Clock and CW Doppler Circuitry Rev. B ...
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SDO_CHA 8 SDI_CHA SCLK_CH A 4 CSB1_CHA 1 2 J501 Figure 79. Evaluation Board Schematic, Power Supply and SPI Interface Circuitry E704 E708 1 1 E703 E707 1 1 E702 E706 1 1 E701 ...
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AD9271 FIFO5: DATA BUS 1 CONNECTOR 6469169-1 P60 1 GNDCD1 GNDCD GNDCD GNDCD GNDCD GNDCD ...
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Figure 81. Evaluation Board Layout, Top Side Figure 82. Evaluation Board Layout, Ground Plane (Layer 2) Rev Page AD9271 ...
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AD9271 Figure 83. Evaluation Board Layout, Power Plane (Layer 3) Figure 84. Evaluation Board Layout, Power Plane (Layer 4) Rev Page ...
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Figure 85. Evaluation Board Layout, Ground Plane (Layer 5) Figure 86. Evaluation Board Layout, Bottom Side Rev Page AD9271 ...
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AD9271 Table 16. Evaluation Board Bill of Materials (BOM) Item Qty. Reference Designator 1 70 C101, C103, C105, C107, C109, C111, C113, C115, C121, C122, C123, C124, C201, C203, C205, C207, C209, C211, C213, C215, C221, C222, C223, C224, C301, ...
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Item Qty. Reference Designator 15 2 J501, P403 16 2 P302, P303 17 2 P405, P406 18 1 P511 19 1 J401 20 13 J101, J102, J103, J104, J201, J202, J203, J204, J301, J402, J403, P401, P402 21 2 P601, ...
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AD9271 Item Qty. Reference Designator 27 3 R303, R422, R423 28 7 R309, R319, R325, R326, R710, R712, R713 29 1 R308 30 2 R310, R336 31 1 R414 32 3 R420, R421, R716 33 1 R335 34 2 R447, ...
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Item Qty. Reference Designator 42 1 U402 43 1 U706 44 2 U704, U707 45 1 U705 46 1 U702 47 1 U703 1 This BOM is RoHS compliant. 2 May use suitable alternative. Device Package Description IC SO8 Dual ...
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... AD9271BSVZRL-50 −40°C to +85°C 1 AD9271BSVZ-40 −40°C to +85°C 1 AD9271BSVZRL-40 −40°C to +85°C 1 AD9271BSVZ-25 −40°C to +85°C 1 AD9271BSVZRL-25 −40°C to +85° RoHS Compliant Part. 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 PIN 1 TOP VIEW ...
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NOTES Rev Page AD9271 ...
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AD9271 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06304-0-5/09(B) Rev Page ...