AD9271BSVZRL-25 Analog Devices Inc, AD9271BSVZRL-25 Datasheet - Page 7

• Manufacturer Part Number: AD9271BSVZRL-25
• Description: IC ADC OCT 12BIT 25MSPS 100-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9271BSVZRL-25

• Number Of Bits: 12
• Sampling Rate (per Second): 25M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 1.06W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Power Dissipation Pd: 150mW
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage: 1.8V
• Sample Rate: 25 MSPS
• Termination Type: SMD
• Supply Voltage Max: 1.9V
• Input Channels Per Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9271-50EBZ - BOARD EVALUATION AD9271 50MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless
otherwise noted.
Table 2.
Parameter
CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (PDWN, STBY, SCLK)
LOGIC INPUT (CSB)
LOGIC INPUT (SDIO)
LOGIC OUTPUT (SDIO)
DIGITAL OUTPUTS (D+, D−), (ANSI-644)
DIGITAL OUTPUTS (D+, D−),
1
2
3
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Specified for LVDS and LVPECL only.
Specified for 13 SDIO pins sharing the same connection.
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage (I
Logic 0 Voltage (I
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
1
OH
OL
= 50 μA)
= 800 μA)
3
OS
OS
2
)
)
OD
OD
)
)
1
1
Full
Full
Full
Full
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Rev. B | Page 7 of 60
Min
250
1.2
1.2
1.2
0
247
1.125
150
1.10
CMOS/LVDS/LVPECL
Typ
1.2
20
1.5
30
0.5
70
0.5
30
2
1.79
LVDS
LVDS
Offset binary
Offset binary
Max
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.30
AD9271
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V