AD9271BSVZRL-25 Analog Devices Inc, AD9271BSVZRL-25 Datasheet - Page 21

• Manufacturer Part Number: AD9271BSVZRL-25
• Description: IC ADC OCT 12BIT 25MSPS 100-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9271BSVZRL-25

• Number Of Bits: 12
• Sampling Rate (per Second): 25M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 1.06W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Power Dissipation Pd: 150mW
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage: 1.8V
• Sample Rate: 25 MSPS
• Termination Type: SMD
• Supply Voltage Max: 1.9V
• Input Channels Per Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9271-50EBZ - BOARD EVALUATION AD9271 50MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CHANNEL OVERVIEW
Each channel contains both a TGC signal path and a CW Doppler
signal path. Common to both signal paths, the LNA provides user-
adjustable input impedance termination. The CW Doppler path
includes a transconductance amplifier and a crosspoint switch. The
TGC path includes a differential X-AMP® VGA, an antialiasing
filter, and an ADC. Figure 40 shows a simplified block diagram
with external components.
The signal path is fully differential throughout to maximize
signal swing and reduce even-order distortion; however, the
LNA is designed to be driven from a single-ended signal source.
Low Noise Amplifier (LNA)
Good noise performance relies on a proprietary ultralow noise
LNA at the beginning of the signal chain, which minimizes the
noise contribution in the following VGA. Active impedance
control optimizes noise performance for applications that benefit
from input impedance matching.
A simplified schematic of the LNA is shown in Figure 41. LI-x is
capacitively coupled to the source. An on-chip bias generator
establishes dc input bias voltages of around 1.4 V and centers
the output common-mode levels at 0.9 V (VDD/2). A capacitor,
C
connected from the LG-x pin to ground.
LG
, of the same value as the input coupling capacitor, C
SWITCH
T/R
CS
Figure 41. Simplified LNA Schematic
CSH
SWITCH
LI-x
T/R
VO+
VCM
CS
CFB
CSH
CFB RFB2
AVDD2
RFB1
CLG
RFB1
RFB2
LO-x
LOSW-x
LI-x
LG-x
Figure 40. Simplified Block Diagram of a Single Channel
VCM
LNA
VO–
LOSW-x
S
LO-x
LG-x
, is
CLG
Rev. B | Page 21 of 60
INTERPOLATOR
ATTENUATOR
–30dB TO 0dB
g
m
GAIN
The LNA supports differential output voltages as high as 2 V p-p
with positive and negative excursions of ±0.5 V from a common-
mode voltage of 0.9 V. The LNA differential gain sets the maximum
input signal before saturation. One of three gains is set through
the SPI. The corresponding input full scale for the gain settings
of 5, 6, or 8 is 400 mV p-p, 333 mV p-p, and 250 mV p-p,
respectively. Overload protection ensures quick recovery time
from large input voltages. Because the inputs are capacitively
coupled to a bias voltage near midsupply, very large inputs can
be handled without interacting with the ESD protection.
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-referred
noise voltage of 1.2 nV/√Hz. This is achieved with a current
consumption of only 16 mA per channel (30 mW). On-chip
resistor matching results in precise single-ended gains, which
are critical for accurate impedance control. The use of a fully
differential topology and negative feedback minimizes distortion.
Low HD2 is particularly important in second-harmonic ultrasound
imaging applications. Differential signaling enables smaller swings
at each output, further reducing third-order distortion.
Active Impedance Matching
The LNA consists of a single-ended voltage gain amplifier with
differential outputs and the negative output externally available.
For example, with a fixed gain of 6× (15.6 dB), an active input
termination is synthesized by connecting a feedback resistor
between the negative output pin, LO-x, and the positive input
pin, LI-x. This technique is well known and results in the input
resistance shown in Equation 1:
where A/2 is the single-ended gain or the gain from the LI-x
inputs to the LO-x outputs.
SWITCH
ARRAY
TO
+24dB
R
IN
=
1 ( A
R
+
FB
AAF
) 2
PIPELINE
12-BIT
ADC
AD9271
SERIAL
LVDS
CDWx+
CDWx–
DOUTx–
DOUTx+
AD9271
(1)