AD9271BSVZRL-25 Analog Devices Inc, AD9271BSVZRL-25 Datasheet - Page 32

• Manufacturer Part Number: AD9271BSVZRL-25
• Description: IC ADC OCT 12BIT 25MSPS 100-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9271BSVZRL-25

• Number Of Bits: 12
• Sampling Rate (per Second): 25M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 1.06W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Power Dissipation Pd: 150mW
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage: 1.8V
• Sample Rate: 25 MSPS
• Termination Type: SMD
• Supply Voltage Max: 1.9V
• Input Channels Per Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9271-50EBZ - BOARD EVALUATION AD9271 50MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9271
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 9.
To change the output data format to twos complement, see the
Memory Map section.
Table 9. Digital Output Coding
Code
4095
2048
2047
0
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
Table 10. Flexible Output Test Modes
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1
All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
(VIN+) − (VIN−),
Input Span = 2 V p-p (V)
+1.00
0.00
−0.000488
−1.00
Off (default)
User input
Pattern Name
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
PN sequence long
PN sequence short
One-/zero-word toggle
1-/0-bit toggle
1× sync
One bit high
Mixed bit frequency
Digital Output Offset Binary
(D11 ... D0)
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
1
1
Digital Output Word 1
N/A
1000 0000 (8 bits)
10 0000 0000 (10 bits)
1000 0000 0000 (12 bits)
10 0000 0000 0000 (14 bits)
1111 1111 (8 bits)
11 1111 1111 (10 bits)
1111 1111 1111 (12 bits)
11 1111 1111 1111 (14 bits)
0000 0000 (8 bits)
00 0000 0000 (10 bits)
0000 0000 0000 (12 bits)
00 0000 0000 0000 (14 bits)
1010 1010 (8 bits)
10 1010 1010 (10 bits)
1010 1010 1010 (12 bits)
10 1010 1010 1010 (14 bits)
N/A
N/A
1111 1111 (8 bits)
11 1111 1111 (10 bits)
1111 1111 1111 (12 bits)
11 1111 1111 1111 (14 bits)
Register 0x19 and Register 0x1A
1010 1010 (8 bits)
10 1010 1010 (10 bits)
1010 1010 1010 (12 bits)
10 1010 1010 1010 (14 bits)
0000 1111 (8 bits)
00 0001 1111 (10 bits)
0000 0011 1111 (12 bits)
00 0000 0111 1111 (14 bits)
1000 0000 (8 bits)
10 0000 0000 (10 bits)
1000 0000 0000 (12 bits)
10 0000 0000 0000 (14 bits)
1010 0011 (8 bits)
10 0110 0011 (10 bits)
1010 0011 0011 (12 bits)
10 1000 0110 0111 (14 bits)
Rev. B | Page 32 of 60
times the sample clock rate, with a maximum of 600 Mbps
(12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required for
a specific application. See the Memory Map section for details
on enabling this feature.
Two output clocks are provided to assist in capturing data from
the AD9271. DCO± is used to clock the output data and is equal
to six times the sampling clock rate. Data is clocked out of the
AD9271 and must be captured on the rising and falling edges of
the DCO± that supports double data rate (DDR) capturing. The
frame clock output (FCO±) is used to signal the start of a new
output byte and is equal to the sampling clock rate. See the
timing diagram shown in Figure 2 for more information.
Digital Output Word 2
N/A
Same
Same
Same
0101 0101 (8 bits)
01 0101 0101 (10 bits)
0101 0101 0101 (12 bits)
01 0101 0101 0101 (14 bits)
N/A
N/A
0000 0000 (8 bits)
00 0000 0000 (10 bits)
0000 0000 0000 (12 bits)
00 0000 0000 0000 (14 bits)
Register 0x1B and Register 0x1C
N/A
N/A
N/A
N/A
Subject to Data
Format Select
N/A
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No