AD9271BSVZRL-25 Analog Devices Inc, AD9271BSVZRL-25 Datasheet - Page 28

• Manufacturer Part Number: AD9271BSVZRL-25
• Description: IC ADC OCT 12BIT 25MSPS 100-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9271BSVZRL-25

• Number Of Bits: 12
• Sampling Rate (per Second): 25M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 1.06W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Power Dissipation Pd: 150mW
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage: 1.8V
• Sample Rate: 25 MSPS
• Termination Type: SMD
• Supply Voltage Max: 1.9V
• Input Channels Per Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9271-50EBZ - BOARD EVALUATION AD9271 50MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9271
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9271 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 54 shows the preferred method for clocking the AD9271.
A low jitter clock source, such as the Valpey Fisher oscillator
VFAC3-BHL-50MHz, is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9271 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9271, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 55. The AD951x family of clock drivers offers excellent
jitter performance.
*
*
50Ω RESISTOR IS OPTIONAL.
50Ω RESISTOR IS OPTIONAL.
EN
EN
VFAC3
VFAC3
3.3V
EN
3.3V
OUT
VFAC3
OUT
3.3V
OUT
50Ω
50Ω
Figure 54. Transformer-Coupled Differential Clock
*
50Ω 100Ω
0.1µF
*
0.1µF
0.1µF
Figure 56. Differential LVDS Sample Clock
Figure 55. Differential PECL Sample Clock
0.1µF
0.1µF
CLK
CLK
ADT1-1WT, 1:1Z
LVDS DRIVER
MINI-CIRCUITS
CLK
CLK
AD951x FAMILY
PECL DRIVER
XFMR
0.1µF
AD951x FAMILY
240Ω
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
240Ω
100Ω
0.1µF
0.1µF
100Ω
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9271
CLK+
CLK–
AD9271
AD9271
ADC
ADC
ADC
Rev. B | Page 28 of 60
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 57). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9271 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9271. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
due only to aperture jitter (t
*
50Ω RESISTOR IS OPTIONAL.
*
50Ω RESISTOR IS OPTIONAL.
EN
VFAC3
EN
3.3V
VFAC3
SNR Degradation = 20 × log 10[1/2 × π × f
OUT
3.3V
OUT
Figure 57. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
Figure 58. Single-Ended 3.3 V CMOS Sample Clock
0.1µF
50Ω
50Ω
0.1µF
0.1µF
*
*
CLK
CLK
CMOS DRIVER
CLK
CLK
CMOS DRIVER
AD951x FAMILY
AD951x FAMILY
J
) can be calculated by
0.1µF
OPTIONAL
OPTIONAL
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
A
× t
CLK+
CLK–
AD9271
CLK+
CLK–
J
]
AD9271
ADC
ADC
A
)