MT47H32M16BN-37E:D Micron Technology Inc, MT47H32M16BN-37E:D Datasheet - Page 6
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MT47H32M16BN-37E:D
Manufacturer Part Number
MT47H32M16BN-37E:D
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H32M16BN-37ED.pdf
(139 pages)
Specifications of MT47H32M16BN-37E:D
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
500ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
205mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H32M16BN-37E:D
Manufacturer:
MICRON
Quantity:
489
Company:
Part Number:
MT47H32M16BN-37E:D
Manufacturer:
MICRON
Quantity:
319
Company:
Part Number:
MT47H32M16BN-37E:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
512Mb: x4, x8, x16 DDR2 SDRAM
List of Tables
Table 1: Key Timing Parameters ...................................................................................................................... 2
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 17
Table 4: Input Capacitance ............................................................................................................................ 26
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 27
Table 6: Temperature Limits .......................................................................................................................... 28
Table 7: Thermal Impedance ......................................................................................................................... 29
Table 8: General Idd Parameters .................................................................................................................... 30
Table 9: Idd7 Timing Patterns (4-Bank Interleave READ Operation) ................................................................ 31
Table 10: DDR2 Idd Specifications and Conditions ........................................................................................ 32
Table 11: AC Operating Specifications and Conditions .................................................................................... 35
Table 12: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 46
Table 13: ODT DC Electrical Characteristics ................................................................................................... 47
Table 14: Input DC Logic Levels ..................................................................................................................... 48
Table 15: Input AC Logic Levels ..................................................................................................................... 48
Table 16: Differential Input Logic Levels ........................................................................................................ 49
Table 17: Differential AC Output Parameters .................................................................................................. 51
Table 18: Output DC Current Drive ................................................................................................................ 51
Table 19: Output Characteristics .................................................................................................................... 52
Table 20: Full Strength Pull-Down Current (mA) ............................................................................................ 53
Table 21: Full Strength Pull-Up Current (mA) ................................................................................................. 54
Table 22: Reduced Strength Pull-Down Current (mA) ..................................................................................... 55
Table 23: Reduced Strength Pull-Up Current (mA) .......................................................................................... 56
Table 24: Input Clamp Characteristics ........................................................................................................... 57
Table 25: Address and Control Balls ............................................................................................................... 58
Table 26: Clock, Data, Strobe, and Mask Balls ................................................................................................. 58
Table 27: AC Input Test Conditions ................................................................................................................ 59
t
t
Table 28: DDR2-400/533 Setup and Hold Time Derating Values (
IS and
IH) ................................................... 61
t
t
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values (
IS and
IH) .......................................... 62
t
t
Table 30: DDR2-400/533
DS,
DH Derating Values with Differential Strobe ..................................................... 65
t
t
Table 31: DDR2-667/800/1066
DS,
DH Derating Values with Differential Strobe ............................................ 67
t
t
Table 32: Single-Ended DQS Slew Rate Derating Values Using
DS
and
DH
.................................................. 68
b
b
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at Vref) at DDR2-667 ...................................... 68
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at Vref) at DDR2-533 ...................................... 69
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at Vref) at DDR2-400 ...................................... 69
Table 36: Truth Table – DDR2 Commands ..................................................................................................... 74
Table 37: Truth Table – Current State Bank n – Command to Bank n ............................................................... 75
Table 38: Truth Table – Current State Bank n – Command to Bank m .............................................................. 77
Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 78
Table 40: Burst Definition .............................................................................................................................. 83
Table 41: READ Using Concurrent Auto Precharge ........................................................................................ 104
Table 42: WRITE Using Concurrent Auto Precharge ....................................................................................... 110
Table 43: Truth Table – CKE ......................................................................................................................... 125
6
PDF: 09005aef82f1e6e2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Rev. M 9/08 EN
© 2004 Micron Technology, Inc. All rights reserved.