MT47H32M16BN-37E:D Micron Technology Inc, MT47H32M16BN-37E:D Datasheet - Page 7
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MT47H32M16BN-37E:D
Manufacturer Part Number
MT47H32M16BN-37E:D
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H32M16BN-37ED.pdf
(139 pages)
Specifications of MT47H32M16BN-37E:D
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
500ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
205mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H32M16BN-37E:D
Manufacturer:
MICRON
Quantity:
489
Company:
Part Number:
MT47H32M16BN-37E:D
Manufacturer:
MICRON
Quantity:
319
Company:
Part Number:
MT47H32M16BN-37E:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
List of Figures
Figure 1: 512Mb DDR2 Part Numbers .............................................................................................................. 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 128 Meg x 4 Functional Block Diagram ............................................................................................. 12
Figure 4: 64 Meg x 8 Functional Block Diagram .............................................................................................. 13
Figure 5: 32 Meg x 16 Functional Block Diagram ............................................................................................. 14
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 15
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 16
Figure 8: 84-Ball FBGA (12mm x 12.5mm) – x16 .............................................................................................. 20
Figure 9: 84-Ball FBGA (10mm x 12.5mm) – x16 .............................................................................................. 21
Figure 10: 84-Ball FBGA (8mm x 12.5mm) – x16 .............................................................................................. 22
Figure 11: 60-Ball FBGA (12mm x 10mm) – x4, x8 ............................................................................................ 23
Figure 12: 60-Ball FBGA (10mm x 10mm) – x4, x8 ............................................................................................ 24
Figure 13: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................. 25
Figure 14: Example Temperature Test Point Location ..................................................................................... 28
Figure 15: Single-Ended Input Signal Levels ................................................................................................... 48
Figure 16: Differential Input Signal Levels ...................................................................................................... 49
Figure 17: Differential Output Signal Levels .................................................................................................... 51
Figure 18: Output Slew Rate Load .................................................................................................................. 52
Figure 19: Full Strength Pull-Down Characteristics ......................................................................................... 53
Figure 20: Full Strength Pull-Up Characteristics ............................................................................................. 54
Figure 21: Reduced Strength Pull-Down Characteristics ................................................................................. 55
Figure 22: Reduced Strength Pull-Up Characteristics ...................................................................................... 56
Figure 23: Input Clamp Characteristics .......................................................................................................... 57
Figure 24: Overshoot ..................................................................................................................................... 58
Figure 25: Undershoot .................................................................................................................................. 58
Figure 26: Nominal Slew Rate for
Figure 27: Tangent Line for
Figure 28: Nominal Slew Rate for
Figure 29: Tangent Line for
Figure 30: Nominal Slew Rate for
Figure 31: Tangent Line for
Figure 32: Nominal Slew Rate for
Figure 33: Tangent Line for
Figure 34: AC Input Test Signal Waveform Command/Address Balls ............................................................... 72
Figure 35: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 72
Figure 36: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 73
Figure 37: AC Input Test Signal Waveform (Differential) ................................................................................. 73
Figure 38: MR Definition ............................................................................................................................... 81
Figure 39: CL ................................................................................................................................................ 85
Figure 40: EMR Definition ............................................................................................................................. 86
Figure 41: READ Latency ............................................................................................................................... 89
Figure 42: WRITE Latency ............................................................................................................................. 89
Figure 43: EMR2 Definition ........................................................................................................................... 90
Figure 44: EMR3 Definition ........................................................................................................................... 91
Figure 45: DDR2 Power-Up and Initialization ................................................................................................. 93
Figure 46: Example: Meeting
Figure 47: Multibank Activate Restriction ....................................................................................................... 97
Figure 48: READ Latency ............................................................................................................................... 99
Figure 49: Consecutive READ Bursts ............................................................................................................. 100
Figure 50: Nonconsecutive READ Bursts ....................................................................................................... 101
PDF: 09005aef82f1e6e2
Rev. M 9/08 EN
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t
t
t
IS ....................................................................................................................... 63
IH ...................................................................................................................... 65
DS ...................................................................................................................... 70
DH ..................................................................................................................... 71
t
RRD (MIN) and
t
t
t
t
IS .............................................................................................................. 63
IH .............................................................................................................. 64
DS ............................................................................................................. 70
DH ............................................................................................................ 71
t
RCD (MIN) .............................................................................. 96
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.