PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 129

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

DMXAD
Semiconductor Group
5) PCSR:DRE has to be set to ‘1’.
6) PMOD:PSM has to be set to ’1’.
Demultiplexed Address.
If set to '0' the demultiplexed addresses are also valid in the multiplexed
P-interface mode.
PCSR:URE has to be set to ‘1’.
When provided with a 2 MHz PDC, the ELIC internally generates a
4 MHz clock.
Since the clock shift capabilities (provided by register bits PCSR:DRCS
and PCSR:ADSR0) apply to the internal 4 MHz clock, the frame can thus
be shifted with a resolution of a half bit.
Figure 55
Timing Relation Between Internal and External Clock
The frame signal PFS must always be sampled with the rising edge of
PDC. The set-up and hold times of PFS are still valid respected to
external PDC.
4 MHz Clock
2 MHz PDC
Internal
EPIC
Core
R
ELIC
4 MHz
R
129
x2
Detailed Register Description
RxD#, TxD# (2 Mbit/s)
PDC = 2 MHz
ITS06897
PEB 20550
PEF 20550
01.96