PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 275

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 96
5.4.4
When a channel is switched from an input time slot (e.g. from the PCM interface) to an
output time slot (e.g. to the CFI), it is sometimes useful to know the frame delay
introduced by this connection. This is of prime importance for example if channels having
a bandwidth of n
the ELIC. If all 6 time slots of an H0 channel are not submitted to the same frame delay,
time slot integrity is no longer maintained.
Since the ELIC has only a one frame buffer, the switching delay depends mainly on the
location of the output time slot with respect to the input time slot. If there is ‘enough’ time
between the two locations, the ELIC switches the input data to the output data within the
same frame (see figure 96 a)). If the time between the two locations is too small or if the
output time slot is later in time than the input time slot, the data received in frame N will
only be transmitted in frame N + 1 or even N + 2 (see figure 96 b)) and figure 96 c)).
Semiconductor Group
a) Switching Delay : 0 Frames
Input Frame
Output Frame
b) Switching Delay : 1 Frames
Input Frame
Output Frame
c) Switching Delay : 2 Frames
Input Frame
Output Frame
Switching Delays
64 kBit/s (e.g. H0 channels: 6
N
N
N
N
N
N
275
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
64 = 384 kBit/s) shall be switched by
N + 2
N + 2
N + 2
N + 2
N + 2
N + 2
Application Hints
+
PEB 20550
PEF 20550
ITD08075
01.96