PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 172

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CM1..0
Note: When bus configuration with direct connection of multiple ELIC’s is used open
ITF
Note: ITF has to be set 0 if clock mode 3 is used.
CM2
Note: Clock mode 3 is only applicable for SACCO-A in combination with the D-channel
Semiconductor Group
drain option is still recommended.
The push-pull option with bus configuration can only be used if an external tri-state
buffer is placed between TXDA / TXDB and the bus.
Due to the delay of TSCA / TSCB in this mode (see description of bits SOC(0:1)
in register CCR2 (chapter 4.7.9)) these signals cannot directly be used to enable
this buffer.
arbiter.
Up to Version 1.2 when selecting a bus configuration only the open
drain option must be selected.
Compared to the Version 1.2 the Version 1.3 provides new features:
Push-pull operation may be selected in bus configuration (up to Version 1.2
only open drain):
• When active TXDA / TXDB outputs serial data in push-pull-mode
• When inactive (interframe or inactive timeslots) TXDA / TXDB outputs ’1’
Inter frame Time Fill.
Determines the "no data to send" state of the transmit data pin (TxDA/B).
0… continuous IDLE-sequences are output ('11111111' bit pattern).
1… continuous FLAG-sequences are output ('01111110' bit pattern). In a bus
Clock rate.
0…single rate data clock
1…double rate data clock
Clock Mode.
Determines the mode in which the data clock is forwarded toward the
receiver/transmitter.
00…clock mode 0:
01…clock mode 1:
10…clock mode 2:
11…clock mode 3:
In a bus configuration (CCR1:SC0 = 1) ITF is implicitly set to '0'
(continuous '1's are transmitted).
configuration (CCR1:SC0 = 1) ITF is implicitly set to '0' (continuous '1's
are transmitted).
external data clock, permanently enabled.
external data clock, gated by an enable strobe
forwarded via pin HFS.
external data clock, programmable time slot
assignment,
forwarded via pin HFS.
internal data clock derived from the CFI, gated
by an internally generated enable strobe.
172
frame
Detailed Register Description
synchronization
PEB 20550
PEF 20550
pulse
01.96