PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 146

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

b) Pre-processed Applications
Downstream:
Application
Decentral D-channel handling
Central D-channel handling
6-bit Signaling (e.g. analog IOM)
8-bit Signaling (e.g. SLD)
D-Channel handling by SACCO-A
with ELIC-arbiter
Upstream:
Application
Decentral D-channel handling
Central D-channel handling
6-bit Signaling (e.g. analog IOM)
8-bit Signaling (e.g. SLD)
All code combinations are also valid
for ELIC-arbiter operation.
c) P-access Applications
MACR:
5. Control-reading the upstream or downstream CM-code.
MACR:
Semiconductor Group
0
1
Setting CMC = 1001, initializes the corresponding CFI time slot to be
accessed by the P. Concurrently, the datum in MADR is written (as 8-bit
CFI-idle code) to the CM-data field. The content of the CM-data field is
directly exchanged with the corresponding time slot.
Note that once the CM-code field has been initialized, the CM-data field can
be written and read as described in chapter 3.
The CM-code can then be read out of the 4 LSBs of the MADR-register.
1
1
1
1
1
1
CMC = 1000
CMC = 1010
CMC = 1010
CMC = 1000
CMC = 1010
CMC = 1011
Even CM Address
CMC = 1010
CMC = 1010
Even CM Address
CMC = 1000
146
1
0
Detailed Register Description
0
0
CMC = 1011
CMC = 0000
Odd CM Address
CMC = PCM-code for a
2-bit subtime slot
CMC = 1011
CMC = 1011
CMC = 1011
Odd CM Address
CMC = PCM-code for a
2-bit subtime slot
CMC = 1010
CMC = 1011
0
0
PEB 20550
PEF 20550
1
0
01.96