PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 55

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

transfer ((k
CSS), if there are further bytes to transfer (figure 29). When a fast DMA-controller is
used (> 16 MHz), byte n (or bytes k
Figure 26
Timing Diagram for DMA-Transfers (fast) Transmit (n < 32, remainder of a long
message or n = k
Figure 27
Timing Diagram for DMA-Transfers (slow) Transmit (n < 32, remainder of a long
message or n = k
In receive direction the behavior of pin DRQR is implemented correspondingly. If k
bytes are transferred, pin DRQR is deactivated with the rising edge of RD of DMA-
However, if 4, 8, 16 or 32 bytes have to be transferred (only these discrete values are
possible in receive direction), DRQR is deactivated with the falling edge of RD
(figure 30).
Semiconductor Group
32)
1) and it is activated again with the next rising edge of DACK (or
32)
32)
DRQT
WR
CSS,
DACK
Cycle
DRQT
WR
CSS,
DACK
Cycle
n-2
32) will be transferred immediately (figure 28).
n-2
n-1
55
n-1
n
ITD05825
Functional Description
n
ITD05826
PEB 20550
PEF 20550
01.96
32