PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 234

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2) In CFI mode 0, with a frame consisting of 32 timeslots, the following timing
The CBSR:CUS bits must therefore be set to ‘0100’, according to figure 77.
The complete value for CBSR is: CBSR = 04
Finally, the CMD2 register bits must be set to
FC2 … 0 = 011, COC = 0, CXF = 1, CRR = 0, CBN9 … 8 = 00, i.e. CMD2 = 68
Figure 81
Timing Signals for CFI Bit Shift Example 2
The framing signal source FSC shall mark CFI timeslot 4, bit 1 in downstream direction
and CFI timeslot 0, bit 5 in upstream direction. The data shall be transmitted with the
rising CRCL edge and sampled with the rising CRCL edge. The FSC signal shall be
sampled with the rising DCL edge.
The following CFI register values result:
Since FSC marks the downstream bit 1, the CBSR:CDS bits must be set to ‘000’,
according to table 34.
If the CBSR:CDS bits are set to ‘000’, FSC marks the timeslot TSN – 1, according to
table 34.
FSC shall mark CFI timeslot 4, i.e. TSN – 1 = 4, or TSN = 4 + 1 = 5
Semiconductor Group
FSC
DCL
DD#
Required
Offset in
Downstream
Direction
Required
Offset in
Upstream
Direction
DU#
relationship between the framing signal source FSC and the data signals is required:
Bit 3
Bit 7
Bit 2
0
Time-Slot 4
Bit 6
1
Start of Internal Frame
TS4,
Bit 1
Bit 1
TS0, Bit 5
Bit 5
Time-Slot 0
Bit 0
234
H
Bit 4
Bit 7
Bit 3
Time-Slot 5
Bit 6
Bit 2
Application Hints
Bit 5
CMD2
CMD1 CSM = 1
CFI Mode 0
CMD2 CRR = 1
PEB 20550
PEF 20550
:
:
:
CXF
H
ITT08060
=
01.96
0