PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 249

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

W:MACR
W:MACR
The MADR bits MD7 … MD0 control the PCM timeslot bit positions 7 … 0 in the
following way:
MD7 … MD4 are not used (don’t care);
MD3 … MD0 select between the states high impedance (MD# = 0) or low impedance
(MD# = 1)
Timeslot Bit Position:
MADR Bits:
The Procedure for Writing to a Single PCM Tristate Field is
W:MADR
W:MAAR
The Procedure for Reading Back a (Single) PCM Tristate Field Location is
W:MAAR
wait for STAR:MAC = 0
R:MADR
The Procedure for Writing to all PCM Tristate Field Positions is
W:MADR
W:MACR
1
Semiconductor Group
The U/D bit of MAAR will implicitly be set to 1.
= X X X X MD3 MD2 MD1 MD0
= address of the desired (upstream)
= 0110 000
= address of the desired (upstream)
= E0
= X X X X MD3 MD2 MD1 MD0
= 0110 1000
= X X X X MD3 MD2 MD1 MD0
H
B
7
B
= 60
MD3
= 68
H
H
6
5
249
MD2
B
B
B
1)
1)
4
PCM timeslot according to figure 84
PCM timeslot according to figure 84
3
MD1
2
Application Hints
PEB 20550
1
PEF 20550
MD0
01.96
0