PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 48

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 6
Boundary Scan Sequence (cont’d)
Boundary
Scan Number
TDI
64
65
66
67
68
69
70
Code
000
001
010
011
111
Others
63
2.2.5.2 TAP-Controller
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG-standard: IEEE Std. 1149.1. Transitions on the pin TMS cause the TAP-controller
to perform a state change. Following the standard definition five instructions are
executable.
Table 7
TAP-Controller Instructions
EXTEST is used to examine the board interconnections.
When the TAP-controller is in the state "update DR", all output pins are updated with the
falling edge of TCK. When it has entered state "capture DR" the levels of all input pins
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
Semiconductor Group
Pin Number Pin Name
64
65
66
67
68
69
70
71
Instruction
EXTEST
INTEST
SAMPLE/PRELOAD
IDCODE
BYPASS
–
TSC1
TxD1
TSC2
TxD2
TSC3
TxD3
PDC
PFS
48
Type
O
O
O
O
O
O
I
I
Function
External testing
Internal testing
Snap-shot testing
Reading ID-code
Bypass operation
Bypass operation
Number of
Scan Cells
2
2
2
2
2
2
1
1
Functional Description
Default
Value
00
00
00
00
00
00
0
0
PEB 20550
PEF 20550
01.96