ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 107

• Manufacturer Part Number: ST7265XEVALMS
• Manufacturer: STMicroelectronics

Specifications of ST7265XEVALMS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

I²C SINGLE MASTER BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The speed of the I
between Standard (up to 100KHz) and Fast I
(up to 400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 63. I
SDA or SDAI
SCL or SCLI
2
C Interface Block Diagram
2
C interface may be selected
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
DATA CONTROL
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL REGISTER (CR)
2
C
The SCL frequency (F
grammable clock divider which depends on the
I
When the I2C cell is enabled, the SDA and SCL
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistance
used depends on the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
2
C bus mode.
DATA SHIFT REGISTER
DATA REGISTER (DR)
CONTROL LOGIC
INTERRUPT
scl
) is controlled by a pro-
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