ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 109
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
ST7265XEVALMS
Manufacturer Part Number
ST7265XEVALMS
Description
Manufacturer
STMicroelectronics
Datasheet
1.ST7265XEVALMS.pdf
(163 pages)
Specifications of ST7265XEVALMS
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 109 of 163
- Download datasheet (4Mb)
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
Figure 64. Transfer Sequencing
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
Master transmitter:
Master receiver:
S
S
EV1: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV2: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV4: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV1
EV1
Address
Address
A
A
EV2
EV2 EV4
Data1
Data1
A
EV3
A
EV4
Data2
Data2
A
EV3
A
EV4
.....
.....
DataN
DataN
NA
EV3
A
ST7265x
EV4
P
109/163
P