ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 42

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ST7265XEVALMS

Manufacturer Part Number
ST7265XEVALMS
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7265XEVALMS

Lead Free Status / Rohs Status
Supplier Unconfirmed
ST7265x
INTERRUPTS (Cont’d)
Table 9. Dedicated Interrupt Instruction Set
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions
change the current software priority up to the next IRET instruction or one of the previously mentioned
instructions.
In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions
should never be used in an interrupt routine.
Table 10. Interrupt Mapping
42/163
1
HALT
IRET
JRM
JRNM
POP CC
RIM
SIM
TRAP
WFI
Instruction
10
0
1
2
3
4
5
6
7
8
9
Source
ESUSP
RESET
Block
TRAP
PLG
DTC
USB
TIM
ICP
SPI
EI0
EI1
EI2
I
2
C
Entering Halt mode
Interrupt routine return
Jump if I1:0=11
Jump if I1:0<>11
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Wait for interrupt
Reset
Software Interrupt
Flash Start Programming NMI Interrupt (TLI)
Power Management USB Plug/Unplug
External Interrupt Port A
DTC Peripheral Interrupt
USB Peripheral Interrupt
USB End Suspend Interrupt
External Interrupt Port D
I
Timer interrupt
External Interrupt Port C
SPI interrupt
2
C Interrupt
New Description
Description
Pop CC, A, X, PC
I1:0=11 ?
I1:0<>11 ?
Mem => CC
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
Function/Example
USBISTR
USBISTR
Register
SPICSR
DTCSR
I2CSRx
Label
PCR
TSR
N/A
N/A
N/A
N/A
Priority
Highest
Lowest
I1
I1
I1
Priority
Priority
1
1
1
1
1
Order
H
H
H
HALT
from
yes
Exit
yes
yes
yes
yes
yes
yes
yes
no
no
no
no
no
I0
I0
I0
0
0
1
1
0
N
N
N
FFECh-FFEDh
FFFCh-FFFDh
FFEAh-FFEBh
FFFAh-FFFBh
FFEEh-FFEFh
FFFEh-FFFFh
FFE8h-FFE9h
FFE6h-FFE7h
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
Address
Vector
Z
Z
Z
C
C
C