ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 60

• Manufacturer Part Number: ST7265XEVALMS
• Manufacturer: STMicroelectronics

Specifications of ST7265XEVALMS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ST7265x
Data Transfer Coprocessor (Cont’d)
11.2.7 Interrupts
Note: The DTC interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC
register is reset (RIM instruction).
11.2.8 Register Description
DTC CONTROL REGISTER (DTCCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:5 = Reserved. Must be left at reset value.
Bit 4 = ERREN Error Interrupt Enable
This bit is set and cleared by software.
0: Error interrupt disabled
1: Error interrupt enabled
Bit 3 = STOPEN Stop Interrupt Enable
This bit is set and cleared by software.
0: Stop interrupt disabled
1: Stop interrupt enabled
Bit 2 = LOAD Load Enable
This bit is set and cleared by software. It can only
be set while RUN=0.
0: Write access to DTC RAM disabled
1: Write access DTC RAM enabled
Bit 1 = INIT Initialization
This bit is set and cleared by software.
0: Do not copy DTCPR to DTC
1: Copy the DTCPR pointer to DTC
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Interrupt Event
Error
Stop
7
0
0
0
ERROR ERREN
Event
STOP STOPEN
Flag
ERR
EN
STOP
EN
Control
Enable
Bit
LOAD
from
Wait
Exit
Yes
Yes
INIT
from
Exit
Halt
RUN
No
No
0
Bit 0 = RUN START/STOP Control
This bit is set and cleared by software. It can only
be set while LOAD=0. It is also cleared by hard-
ware when STOP=1
0: Stop DTC
1: Start DTC
DTC STATUS REGISTER (DTCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1 = ERROR Error Flag
This bit is set by hardware and cleared by software
reading this register.
0: No Error event occurred
1: Error event occurred (DTC is running)
Bit 0 = STOP Stop Flag
This bit is set by hardware and cleared by software
reading this register.
0: No Stop event occurred
1: Stop event occurred (DTC terminated execution
DTC POINTER REGISTER (DTCPR)
Write Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = PC[7:0] Pointer Register.
This register is written by software. It gives the ad-
dress of an entry point in the protocol software that
has previously been loaded in the DTC RAM.
Note: To start executing the function, after writing
this address, set the INIT bit.
MSB
at the current intruction)
7
7
0
0
0
0
0
0
ERROR
STOP
LSB
0
0