ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 59

• Manufacturer Part Number: ST7265XEVALMS
• Manufacturer: STMicroelectronics

Specifications of ST7265XEVALMS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Transfer Coprocessor (Cont’d)
When the USB interface is used, data transfer is
typically controlled by a host computer.
The ST7 core can also read from and write to the
data buffer of the DTC. Typically, the ST7 controls
the application when the USB not used (autono-
mous mode). The buffer can potentially be ac-
cessed by any one of three requestors, the ST7,
the DTC and the USB. Mastership of the buffer is
not time limited. While a master is accessing the
buffer, other requests will not be acknowleged until
the buffer is freed by the master. If several re-
quests are pending, when the buffer is free it is
granted to the source with the highest priority in
the daisy-chain (fixed by hardware), first the ST7,
secondly the USB and finally the DTC.
Note: Any access by the ST7 to the buffer requires
more cycles than either a DTC or USB access. For
performance reasons, when the USB interface is
exchanging data with the DTC, ST7 accesses
should be avoided if possible.
11.2.3 Loading the Protocol Software
The DTC must first be initialized by loading the
protocol-specific software plug-in (provided by
STMicroelectronics) into the DTC RAM. To do this:
1. Stop the DTC by clearing the RUN bit in the
2. Remove the write protection by setting the
3. Load the (null-terminated) software plug-in in
Figure 35. State Diagram of DTC Operations
DTCCR register
LOAD bit in the DTCCR register
the DTC RAM.
DTC RAM
LOAD=1
LOAD
RUN=0
INIT=0
POINTER
CHANGE
LOAD=0
RUN=0
INIT=1
LOAD=1
INIT=1
LOAD=0
INIT=0
DTC
IDLE
LOAD=0
RUN=0
INIT=0
RUN=0
RUN=1
4. Restore the write protection by clearing the
The DTC is then ready for operation.
11.2.4 Executing the Protocol Functions
To execute any of the software plug-in functions
follow the procedure below:
1. Clear the RUN bit to stop the DTC
2. Select the function by writing its address in the
3. Set the INIT bit in the DTCCR register to copy
4. Clear the INIT bit to return to idle state.
5. Set the RUN bit to start the DTC.
11.2.5 Changing the DTCPR pointer on the fly
As shown in
by writing INIT=1 while the DTC is running
(RUN=1), however if the DTC is executing an in-
ternal interrupt routine, there will be a delay until
interrupt handling is completed.
11.2.6 Low Power Modes
Mode
WAIT
HALT
INIT=0
LOAD bit in the DTCCR register
DTCPR register (refer to the separate docu-
ment for address information).
the DTCPR pointer to the DTC.
ON-THE-FLY
RUNNING
LOAD=0
RUN=1
POINTER
CHANGE
INIT=0
DTC
LOAD=0
RUN=1
INIT=1
Description
No effect on DTC
DTC halted.
Figure
INIT=1
35, the pointer can be changed
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