ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 53

• Manufacturer Part Number: ST7265XEVALMS
• Manufacturer: STMicroelectronics

Specifications of ST7265XEVALMS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

10 MISCELLANEOUS REGISTERS
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = IS1[1:0] ei0 Interrupt sensitivity
Interrupt sensitivity, defined using the IS1[1:0] bits,
is applied to the ei0 interrupts (Port A):
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
1: MCO alternate function enabled (f
Bits 4:3 = IS2[1:0] ei1 Interrupt sensitivity
Interrupt sensitivity, defined using the IS2[1:0] bits,
is applied to the ei1 external interrupts (Port D):
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
IS11 IS10
IS21 IS20
IS11
0
0
1
1
general-purpose I/O)
I/O port)
0
0
1
1
7
IS10 MCO IS21
0
1
0
1
0
1
0
1
External Interrupt Sensitivity
External Interrupt Sensitivity
Falling edge & low level
Falling edge & low level
Rising and falling edge
Rising and falling edge
Falling edge only
Falling edge only
Rising edge only
Rising edge only
IS20
CP1
CPU
CP0 CPEN
output on
0
Bits 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the CPEN bit. These
two bits are set and cleared by software
Caution:
– The ST7 core is not able to read or write in the
– In USB mode, with f
Note:
– A frequency change of the ST7 core does not af-
Bit 0 = CPEN Clock Prescaler Enable
This bit is set and cleared by software. It is used
with the CP[1:0] bits to configure the internal clock
frequency.
0: Default f
1: f
Stand-alone mode
(f
USB mode
(48 MHz PLL)
USB data buffer if the ST7265x is configured at 6
MHz in standalone mode.
accesses the USB data buffer, this may prevent
the USB interface from accessing the buffer, re-
sulting in a USB buffer overrun error. This is be-
cause an access to memory lasts one cycle and
the USB has to send/receive at a fixed baud rate.
fect the frequency of the Data Transfer Coproc-
essor (DTC).
OSC
Operating Mode
CPU
= 12 MHz)
determined by CP[1:0] bits
CPU
used (3 or 6 MHz)
CPU
3 MHz
6 MHz*
1.5 MHz
750 KHz
375 KHz
6 MHz
8 MHz
2 MHz
1 MHz
250 KHz
f
CPU
≤
2 MHz, if the ST7 core
CP1 CP0 CPEN
x
0
1
0
1
x
0
1
0
1
ST7265x
0
0
1
1
0
0
1
1
x
x
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0
1
1
1
1
0
1
1
1
1
1