MT29F1G08ABADAH4:D Micron Technology Inc, MT29F1G08ABADAH4:D Datasheet - Page 45
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MT29F1G08ABADAH4:D
Manufacturer Part Number
MT29F1G08ABADAH4:D
Description
MICMT29F1G08ABADAH4:D 1GB SLC NAND BGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT29F1G08ABADAH4D.pdf
(93 pages)
Specifications of MT29F1G08ABADAH4:D
Cell Type
NAND
Density
8Gb
Interface Type
Parallel
Address Bus
27b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
VFBGA
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
128M
Supply Current
35mA
Mounting
Surface Mount
Pin Count
63
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT29F1G08ABADAH4:D
Manufacturer:
ROHM
Quantity:
1 001
Company:
Part Number:
MT29F1G08ABADAH4:D
Manufacturer:
MICRON
Quantity:
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Company:
Part Number:
MT29F1G08ABADAH4:D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Status Operations
Table 14: Status Register Definition
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
SR Bit
7
6
5
4
3
2
1
0
Program Page
Write protect
Reserved
ARDY
RDY
FAIL
–
–
–
Notes:
Program Page
Each die (LUN) provides its status independently of other die (LUNs) on the same tar-
get through its 8-bit status register.
After the READ STATUS (70h) command is issued, status register output is enabled. The
contents of the status register are returned on I/O[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled,
changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is
not necessary to toggle RE# to see the status register update.
While monitoring the status register to determine when a data transfer from the Flash
array to the data register (
command to disable the status register and enable data output (see Read Operations).
With internal ECC enabled, a READ STATUS command is required after completion of
the data transfer (
Cache Mode
Write protect
FAILC (N - 1)
RDY
1. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.
2. Status register bit 5 is 0 during the actual programming operation. If cache mode is
3. A status register bit defined as Rewrite Recommended signifies that the page includes
4. A status register bit defined as FAIL signifies that an uncorrectable READ error has occur-
FAIL (N)
ARDY
used, this bit will be 1 when all internal operations are complete.
acertain number of READ errors per sector (512B (main) + 4B (spare) + 8B (parity). A re-
writeof this page is recommended. (Up to a 4-bit error has been corrected if internal
ECC was enabled.)
red.
1
–
–
–
cache
2
recommended
Write protect
t
Page Read
R_ECC) to determine whether an uncorrectable read error occurred.
Reserved
Rewrite
ARDY
FAIL
RDY
–
–
4
t
R) is complete, the host must issue the READ MODE (00h)
45
3
Cache Mode
Write protect
Page Read
RDY
ARDY
1
–
–
–
–
–
Micron Technology, Inc. reserves the right to change products or specifications without notice.
cache
2
1Gb x8, x16: NAND Flash Memory
Write protect 0 = Protected
Block Erase
ARDY
RDY
FAIL
–
–
–
–
1 = Not protected
0 = Busy
1 = Ready
Don't Care
Don't Care
0 = Normal or uncorrectable
1 = Rewrite recommended
Don't Care
Don't Care
0 = Successful PROGRAM/
ERASE/READ
1 = Error in PROGRAM/
ERASE
READ
© 2010 Micron Technology, Inc. All rights reserved.
Status Operations
Description