MT29F1G08ABADAH4:D Micron Technology Inc, MT29F1G08ABADAH4:D Datasheet - Page 6
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MT29F1G08ABADAH4:D
Manufacturer Part Number
MT29F1G08ABADAH4:D
Description
MICMT29F1G08ABADAH4:D 1GB SLC NAND BGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT29F1G08ABADAH4D.pdf
(93 pages)
Specifications of MT29F1G08ABADAH4:D
Cell Type
NAND
Density
8Gb
Interface Type
Parallel
Address Bus
27b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
VFBGA
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
128M
Supply Current
35mA
Mounting
Surface Mount
Pin Count
63
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT29F1G08ABADAH4:D
Manufacturer:
ROHM
Quantity:
1 001
Company:
Part Number:
MT29F1G08ABADAH4:D
Manufacturer:
MICRON
Quantity:
2 690
Company:
Part Number:
MT29F1G08ABADAH4:D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
List of Figures
Figure 1: Marketing Part Number Chart .......................................................................................................... 2
Figure 2: 48-Pin TSOP – Type 1, CPL (Top View) ............................................................................................... 8
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ....................................................................................... 10
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 11
Figure 5: 48-Pin TSOP – Type 1, CPL .............................................................................................................. 12
Figure 6: 63-Ball VFBGA (HC) ........................................................................................................................ 13
Figure 7: 63-Ball VFBGA (H4) 9mm x 11mm ................................................................................................... 14
Figure 8: NAND Flash Die (LUN) Functional Block Diagram ........................................................................... 15
Figure 9: Array Organization – x8 ................................................................................................................... 16
Figure 10: Array Organization – x16 ................................................................................................................ 17
Figure 11: Asynchronous Command Latch Cycle ............................................................................................ 19
Figure 12: Asynchronous Address Latch Cycle ................................................................................................ 20
Figure 13: Asynchronous Data Input Cycles ................................................................................................... 21
Figure 14: Asynchronous Data Output Cycles ................................................................................................. 22
Figure 15: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 23
Figure 16: READ/BUSY# Open Drain ............................................................................................................. 24
Figure 17:
Figure 18:
Figure 19: I
Figure 20: I
Figure 21: TC vs. Rp ....................................................................................................................................... 27
Figure 22: R/B# Power-On Behavior ............................................................................................................... 28
Figure 23: RESET (FFh) Operation ................................................................................................................. 31
Figure 24: READ ID (90h) with 00h Address Operation .................................................................................... 32
Figure 25: READ ID (90h) with 20h Address Operation .................................................................................... 32
Figure 26: READ PARAMETER (ECh) Operation .............................................................................................. 35
Figure 27: READ UNIQUE ID (EDh) Operation ............................................................................................... 39
Figure 28: SET FEATURES (EFh) Operation .................................................................................................... 41
Figure 29: GET FEATURES (EEh) Operation ................................................................................................... 42
Figure 30: READ STATUS (70h) Operation ...................................................................................................... 46
Figure 31: RANDOM DATA READ (05h-E0h) Operation .................................................................................. 47
Figure 32: RANDOM DATA INPUT (85h) Operation ........................................................................................ 48
Figure 33: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 49
Figure 34: READ PAGE (00h-30h) Operation ................................................................................................... 52
Figure 35: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 52
Figure 36: READ PAGE CACHE SEQUENTIAL (31h) Operation ........................................................................ 53
Figure 37: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 54
Figure 38: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 55
Figure 39: PROGRAM PAGE (80h-10h) Operaton ............................................................................................ 57
Figure 40: PROGRAM PAGE CACHE (80h-15h) Operation (Start) ..................................................................... 58
Figure 41: PROGRAM PAGE CACHE (80h-15h) Operation (End) ...................................................................... 58
Figure 42: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 59
Figure 43: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ............................................................... 61
Figure 44: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ................... 61
Figure 45: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 62
Figure 46: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ........... 62
Figure 47: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ....................................................... 63
Figure 48: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................. 63
Figure 49: OTP DATA PROGRAM (After Entering OTP Operation Mode) .......................................................... 66
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
t
t
Fall and
Fall and
OL
OL
vs. Rp (V
vs. Rp (1.8V V
t
t
Rise (3.3V V
Rise (1.8V V
CC
= 3.3V V
CC
) ....................................................................................................................... 26
CC
CC
CC
) ................................................................................................................ 25
) ................................................................................................................ 25
) .............................................................................................................. 26
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb x8, x16: NAND Flash Memory
© 2010 Micron Technology, Inc. All rights reserved.
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