EPM7256EGI192-20 Altera, EPM7256EGI192-20 Datasheet - Page 29
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EPM7256EGI192-20
Manufacturer Part Number
EPM7256EGI192-20
Description
IC MAX 7000 CPLD 256 192-PGA
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7256EGI192-20
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
192-PGA
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
83.33MHz
Propagation Delay Time
20ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
192
Package Type
CPGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2356
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7256EGI192-20
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 12. MAX 7000 Timing Model
Notes:
(1)
(2)
Altera Corporation
Only available in MAX 7000E and MAX 7000S devices.
Not available in 44-pin devices.
Delay
Input
t
I N
f
Delay
t
PIA
PIA
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters.
relationship of internal and external delay parameters.
For more infomration, see
Timing).
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
t
Delay
t
t
t
t
t
t
GLOB
SEXP
LAD
LAC
I C
EN
IOE
(1)
MAX 7000 Programmable Logic Device Family Data Sheet
Expander Delay
Application Note 94 (Understanding MAX 7000
Parallel
t
PEXP
Input Delay
Figure 13
Fast
t
F I N
(1)
Register
t
t
t
t
t
t
t
t
Delay
SU
H
PRE
CLR
RD
COMB
FSU
FH
shows the internal timing
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
X1
(2)
(2)
(1)
Delay
I/O
t
I O
29