EPM7256EGI192-20 Altera, EPM7256EGI192-20 Datasheet - Page 8
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EPM7256EGI192-20
Manufacturer Part Number
EPM7256EGI192-20
Description
IC MAX 7000 CPLD 256 192-PGA
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7256EGI192-20
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
192-PGA
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
83.33MHz
Propagation Delay Time
20ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
192
Package Type
CPGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2356
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7256EGI192-20
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 2. MAX 7000E & MAX 7000S Device Block Diagram
8
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/GCLK1
6 to 16 I/O Pins
6 to 16 I/O Pins
INPUT/OE1
Control
Control
Block
Block
I/O
I/O
6
6
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Figure 2
Logic Array Blocks
The MAX 7000 device architecture is based on the linking of high-
performance, flexible, logic array modules called logic array blocks
(LABs). LABs consist of 16-macrocell arrays, as shown in
Multiple LABs are linked together via the programmable interconnect
array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.
LAB A
LAB C
Macrocells
Macrocells
shows the architecture of MAX 7000E and MAX 7000S devices.
33 to 48
1 to 16
6 to16
6 to16
16
16
36
36
PIA
36
36
6 to16
6 to16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Control
Control
Block
Block
I/O
I/O
Altera Corporation
6
6
Figures 1
6 to 16 I/O Pins
6 to 16 I/O Pins
and 2.