EPM7256EGI192-20 Altera, EPM7256EGI192-20 Datasheet - Page 30

IC MAX 7000 CPLD 256 192-PGA

EPM7256EGI192-20

Manufacturer Part Number
EPM7256EGI192-20
Description
IC MAX 7000 CPLD 256 192-PGA
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7256EGI192-20

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
192-PGA
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
83.33MHz
Propagation Delay Time
20ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
192
Package Type
CPGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2356

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7256EGI192-20
Manufacturer:
BB
Quantity:
630
Part Number:
EPM7256EGI192-20
Manufacturer:
ALTERA
Quantity:
893
Part Number:
EPM7256EGI192-20
Manufacturer:
ALTERA
0
Part Number:
EPM7256EGI192-20
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 13. Switching Waveforms
30
t
Inputs are driven at 3 V
for a logic high and 0 V
for a logic low. All timing
characteristics are
measured at 1.5 V.
R
& t
F
< 3 ns.
(Logic Array Output)
Parallel Expander
Shared Expander
Register Output
Input or I/O Pin
Register to PIA
Data or Enable
Clock into PIA
to Logic Array
Global Clock
Logic Array
Logic Array
Logic Array
Logic Array
Output Pin
at Register
PIA Delay
Clock into
Data from
Input Pin
Clock Pin
Register
Clock at
I/O Pin
Output
Global
Delay
Delay
to Pin
Input
Combinatorial Mode
Global Clock Mode
Array Clock Mode
t
t
R
R
t
t
IN
t
t
SU
IN
IO
t
t
ACH
CH
t
t
t
t
H
t
PIA
IN
GLOB
IO
t
RD
t
t
IC
SU
t
PIA
t
t
ACL
t
CL
SEXP
t
H
t
PIA
t
OD
t
LAC
, t
LAD
t
PEXP
t
t
F
F
t
COMB
Altera Corporation
t
CLR
, t
PRE
t
OD
t
OD
t
PIA

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