EPM7256EGI192-20 Altera, EPM7256EGI192-20 Datasheet - Page 33
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EPM7256EGI192-20
Manufacturer Part Number
EPM7256EGI192-20
Description
IC MAX 7000 CPLD 256 192-PGA
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7256EGI192-20
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
192-PGA
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
83.33MHz
Propagation Delay Time
20ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
192
Package Type
CPGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2356
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7256EGI192-20
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 21. MAX 7000 & MAX 7000E External Timing Parameters
Input to non-registered output
I/O input to non-registered output
Global clock setup time
Global clock hold time
Global clock setup time of fast input
Global clock hold time of fast input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear and
preset
Output data hold time after clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Parameter
(2)
(2)
(3)
(5)
(5)
(6)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
MAX 7000 Programmable Logic Device Family Data Sheet
(4)
MAX 7000E (-10P) MAX 7000 (-10)
100.0
100.0
125.0
Min
7.0
0.0
3.0
0.5
4.0
4.0
2.0
3.0
4.0
4.0
4.0
1.0
Note (1)
Speed Grade
Max
10.0
10.0
10.0
10.0
10.0
5.0
MAX 7000E (-10)
100.0
100.0
125.0
Min
8.0
0.0
3.0
0.5
4.0
4.0
3.0
3.0
4.0
4.0
4.0
1.0
Max
10.0
10.0
10.0
10.0
10.0
5
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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