EPM7256EGI192-20 Altera, EPM7256EGI192-20 Datasheet - Page 9
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EPM7256EGI192-20
Manufacturer Part Number
EPM7256EGI192-20
Description
IC MAX 7000 CPLD 256 192-PGA
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7256EGI192-20
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
192-PGA
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
83.33MHz
Propagation Delay Time
20ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
192
Package Type
CPGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2356
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7256EGI192-20
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell
Altera Corporation
36 Signals
from PIA
Logic Array
Product Ter
16 Expander
T T ms
Each LAB is fed by the following signals:
■
■
■
Macrocells
The MAX 7000 macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select
matrix, and the programmable register. The macrocell of EPM7032,
EPM7064, and EPM7096 devices is shown in
Product-
Select
Matrix
Ter
T T m
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used
for fast setup times for MAX 7000E and MAX 7000S devices
Shared Logic
Expanders
Parallel Logic
Expanders
(from other
macrocells)
MAX 7000 Programmable Logic Device Family Data Sheet
Global
Clear
Select
Clear
Global
Clocks
2
VCC
Enable
Clock/
Select
Fast Input
Select
D/T
ENA
Figure
CLRN
PRN
to PIA
Q
Programmable
Register
Register
3.
Bypass
From
I/O pin
To I/O
Control
Block
9