DSPB56364AF100 Freescale Semiconductor, DSPB56364AF100 Datasheet - Page 3

• Manufacturer Part Number: DSPB56364AF100
• Description: IC DSP 24BIT AUD 100MHZ 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56364AF100

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (24 kB)
• On-chip Ram: 11.25kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Freescale Semiconductor
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100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.
Object Code Compatible with the 56000 core.
Data ALU with a 24 × 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic
support.
Program Control with position independent code support and instruction cache support.
Six-channel DMA controller.
PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors
(1 to 16) and power saving clock divider (2
Internal address tracing support and OnCE™ for Hardware/Software debugging.
JTAG port.
Very low-power CMOS design, fully static design with operating frequencies down to DC.
STOP and WAIT low-power standby modes.
1.5K × 24 Bit Y-Data RAM.
1K × 24 Bit X-Data RAM.
8K × 24 Bit Program ROM.
0.5K × 24 Bit Program RAM and 192 × 24 Bit Bootstrap ROM.
0.75K × 24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25K × 24
Bit of Program RAM.
External Memory Expansion Port with 8-bit data bus.
Off-chip expansion up to 2 × 16M × 8-bit word of Data/Program memory when using DRAM.
Off-chip expansion up to 2 × 256k × 8-bit word of Data/Program memory when using SRAM.
Simultaneous glueless interface to SRAM and DRAM.
Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmit and 2
transmit only, master or slave. I
Unused pins of ESAI may be used as GPIO lines.
Serial Host Interface (SHI): SPI and I
24-bit words.
Four dedicated GPIO lines.
Features
Digital Signal Processing Core
On-Chip Memory Configuration
Off-Chip Memory Expansion
Peripheral Modules
DSP56364 Technical Data, Rev. 4.1
2
S, Sony, AC97, network and other programmable protocols.
2
C protocols, 10-word receive FIFO, support for 8, 16 and
i
: i = 0 to 7). Reduces clock noise.
Overview
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