DSPB56364AF100 Freescale Semiconductor, DSPB56364AF100 Datasheet - Page 49

IC DSP 24BIT AUD 100MHZ 100-LQFP

DSPB56364AF100

Manufacturer Part Number
DSPB56364AF100
Description
IC DSP 24BIT AUD 100MHZ 100-LQFP
Manufacturer
Freescale Semiconductor
Series
Symphony™r
Type
Audio Processorr
Datasheet

Specifications of DSPB56364AF100

Interface
Host Interface, I²C, SAI, SPI
Clock Rate
100MHz
Non-volatile Memory
ROM (24 kB)
On-chip Ram
11.25kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPB56364AF100
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
DSPB56364AF100
Manufacturer:
TI
Quantity:
996
Part Number:
DSPB56364AF100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
DSPB56364AF100
Manufacturer:
FREESCALE
Quantity:
20 000
Freescale Semiconductor
1
2
3
4
5
191
192
193
194
195
No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
The number of wait states for out-of-page access is specified in the DCR.
The refresh period is specified in the DCR.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
The asynchronous delays specified in the expressions are valid for DSP56364.
Either t
No.
RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
Random read or write cycle time
RAS assertion to data valid (read)
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
RAS deassertion to RAS assertion
RAS assertion pulse width
CAS assertion to RAS deassertion
RAS assertion to CAS deassertion
CAS assertion pulse width
RAS assertion to CAS assertion
RAS assertion to column address valid
CAS deassertion to RAS assertion
CAS deassertion pulse width
Row address valid to RAS assertion
RAS assertion to row address not valid
RCH
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
or t
RRH
Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States
must be satisfied for read cycles.
Characteristics
Characteristics
3
DSP56364 Technical Data, Rev. 4.1
3
3
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
ROH
t
t
t
RAC
CAC
t
t
RAS
RSH
CSH
CAS
RCD
RAD
CRP
t
ASR
RAH
OFF
GA
GZ
RC
RP
CP
AA
11.5 × T
0.75 × T
8.25 × T
4.75 × T
6.25 × T
9.75 × T
6.25 × T
8.25 × T
4.75 × T
7.75 × T
6.25 × T
6.25 × T
2.75 × T
Expression
10 × T
External Memory Expansion Port (Port A)
5.5 × T
2.75 × T
Expression
3.5 × T
0.25 × T
16 × T
0.0
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
− 7.0
C
C
− 4.0
− 0.3
− 5.7
C
− 5.7
− 5.7
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
C
± 2
± 2
OFF
4
1, 2
and not t
111.0
(continued)
Min
0.0
7.2
160.0
58.5
93.5
58.5
78.5
43.5
33.0
25.5
73.5
58.5
58.5
23.5
Min
0.0
1, 2
GZ
.
Max
93.0
2.5
Max
76.8
41.8
49.3
37.0
29.5
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-33

Related parts for DSPB56364AF100