DSPB56364AF100 Freescale Semiconductor, DSPB56364AF100 Datasheet - Page 47

IC DSP 24BIT AUD 100MHZ 100-LQFP

DSPB56364AF100

Manufacturer Part Number
DSPB56364AF100
Description
IC DSP 24BIT AUD 100MHZ 100-LQFP
Manufacturer
Freescale Semiconductor
Series
Symphony™r
Type
Audio Processorr
Datasheet

Specifications of DSPB56364AF100

Interface
Host Interface, I²C, SAI, SPI
Clock Rate
100MHz
Non-volatile Memory
ROM (24 kB)
On-chip Ram
11.25kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPB56364AF100
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
DSPB56364AF100
Manufacturer:
TI
Quantity:
996
Part Number:
DSPB56364AF100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
DSPB56364AF100
Manufacturer:
FREESCALE
Quantity:
20 000
1
2
3
4
5
Freescale Semiconductor
186
187
188
189
190
191
192
193
194
195
No.
The number of wait states for out-of-page access is specified in the DCR.
The refresh period is specified in the DCR.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
The asynchronous delays specified in the expressions are valid for DSP56364.
Either t
157
158
159
160
161
162
163
No.
CAS assertion to data not valid (write)
RAS assertion to data not valid (write)
WR assertion to CAS assertion
CAS assertion to RAS assertion
(refresh)
RAS deassertion to CAS assertion
(refresh)
RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high
impedance
Random read or write cycle time
RAS assertion to data valid (read)
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
RAS deassertion to RAS assertion
RAS assertion pulse width
RCH
Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States
or t
RRH
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
Characteristics
must be satisfied for read cycles.
Characteristics
3
3
DSP56364 Technical Data, Rev. 4.1
3
Symbol
t
t
t
t
t
WCS
t
DHR
CSR
RPC
ROH
t
t
DH
GA
GZ
3.25 × T
5.75 × T
1.75 × T
0.75 × T
5.5 × T
1.5 × T
8.5 × T
7.5 × T
7.5 × T
Expression
0.25 × T
0.0
Symbol
C
C
C
C
C
t
t
t
t
C
C
C
C
t
RAC
CAC
t
t
RAS
OFF
RC
RP
− 4.3
− 4.0
− 4.0
− 7.5
− 6.5
AA
− 4.0
− 4.0
− 4.0
− 0.3
C
4
124.8
6.25 × T
3.75 × T
4.25 × T
7.75 × T
45.2
83.1
79.0
18.7
22.5
11.1
Min
4.5 × T
0.0
Expression
External Memory Expansion Port (Port A)
66 MHz
12 × T
C
C
C
C
C
− 7.0
106.1
C
− 7.0
− 7.0
− 4.0
− 4.0
Max
3.8
OFF
4
1, 2
and not t
(continued)
102.3
120.0
36.6
67.9
64.5
14.8
17.9
38.5
73.5
Min
Min
0.0
9.1
0.0
1, 2
80 MHz
GZ
.
Max
55.5
30.5
38.0
Max
87.3
3.1
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-31

Related parts for DSPB56364AF100