DSPB56364AF100 Freescale Semiconductor, DSPB56364AF100 Datasheet - Page 62

IC DSP 24BIT AUD 100MHZ 100-LQFP

DSPB56364AF100

Manufacturer Part Number
DSPB56364AF100
Description
IC DSP 24BIT AUD 100MHZ 100-LQFP
Manufacturer
Freescale Semiconductor
Series
Symphony™r
Type
Audio Processorr
Datasheet

Specifications of DSPB56364AF100

Interface
Host Interface, I²C, SAI, SPI
Clock Rate
100MHz
Non-volatile Memory
ROM (24 kB)
On-chip Ram
11.25kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Serial Host Interface (SHI) I
In I
to
The programmed serial clock cycle (T
in order to achieve the desired SCL frequency, as shown in
EXAMPLE:
For DSP clock frequency of 100 MHz (i.e. T
(F
Choosing HRS = 0 gives
Thus the HDM[7:0] value should be programmed to $38 (=56).
3-46
SCL
2
C mode, the user may select a value for the programmed serial clock cycle from
HREQ
= 100 KHz (i.e. T
SDA
SCL
Stop
172
173
174
188
Start
Filters bypassed
Narrow filters enabled
Wide filters enabled
2
SCL
177
C Protocol Timing
Table 3-19 SCL Serial Clock Cycle Generated as Master
T
= 10μs), T
I
HDM 7 0 :
2
CCP
4096
176
6
189
171
×
MSB
[
=
×
T
179
DSP56364 Technical Data, Rev. 4.1
I
C
2
T
10μs 2.5
CCP
R
(
C
]
if HDMS 5 0 :
= 1000ns), with filters bypassed
Figure 3-22 I
(
=
if HDMS 7 0 :
), SCL rise time (T
186
C
(
T
T
T
178
8930ns
= 10ns), operating in a standard-mode I
I
I
I
2
2
2
CCP + 2.5
CCP + 2.5
CCP + 2.5
175
×
[
10ns 45ns
[
)
2
C Timing
184
]
(
2
×
×
×
=
]
×
182
=
T
T
T
Table
$
180
LSB
C
C
C
02
10ns
$
R
+ 45ns +
+ 135ns +
+ 223ns +
FF
), and the filters selected should be chosen
and HRS
3-19.
and HRS
×
1000ns
8
T
) 1
T
T
R
R
R
ACK
=
=
=
=
1
)
893ns
55.8
0
187
183
)
Freescale Semiconductor
Stop
2
C environment
AA0275

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