EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 118

• Manufacturer Part Number: EP3C40F484C8N
• Description: IC CYCLONE III FPGA 40K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 331
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2475
• Family Type: Cyclone III
• No. Of I/o's: 331
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2492

6–18
Table 6–6. Number of VREF Pins Per I/O Banks for Cyclone III and Cyclone III LS Devices (Part 1 of 2)
Cyclone III Device Handbook, Volume 1
Family
f
f
1
EP3C120
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
Device
EP3C5
When VREF pins are used as regular I/Os, they have higher pin capacitance than
regular user I/O pins. This has an impact on the timing if the pins are used as inputs
and outputs.
For more information about VREF pin capacitance, refer to the pin capacitance section
in the
For more information about how to identify V
Device Family Pin-Out files or the Quartus II Pin Planner tool.
Table 6–6
Cyclone III LS devices.
Cyclone III Device Data Sheet
lists the number of VREF pins in each I/O bank for Cyclone III and
Package
MBGA
MBGA
MBGA
EQFP
FBGA
EQFP
FBGA
EQFP
PQFP
FBGA
FBGA
EQFP
PQFP
FBGA
FBGA
PQFP
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Pin Count
144
164
256
144
164
256
144
164
240
256
484
144
240
256
324
240
324
484
780
484
780
484
780
484
780
and
1
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
Cyclone III LS Device Data Sheet
2
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
Chapter 6: I/O Features in the Cyclone III Device Family
REF
3
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
groups, refer to the Cyclone III
I/O Banks
4
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
© December 2009 Altera Corporation
5
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
6
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
chapters.
7
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
I/O Banks
8
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3