EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 147

• Manufacturer Part Number: EP3C40F484C8N
• Description: IC CYCLONE III FPGA 40K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 331
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2475
• Family Type: Cyclone III
• No. Of I/o's: 331
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2492

Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 1 of 4)
© January 2010 Altera Corporation
EP3C5
EP3C10
Device
144-pin
164-pin MBGA
256-pin FineLine
BGA/256-pin Ultra
FineLine BGA
144-pin EQFP
164-pin MBGA
256-pin FineLine
BGA/256-pin Ultra
FineLine BGA
In the ×9, ×18, and ×36 modes, a pair of complementary DQS pins (CQ and CQ#)
drives up to 9, 18, or 36 DQ pins, respectively, in the group, to support one, two, or
four parity bits and the corresponding data bits. The ×9, ×18, and ×36 modes support
the QDR II memory interface. CQ# is the inverted read-clock signal which is
connected to the complementary data strobe (DQS or CQ#) pin. You can use any
unused DQ pins as regular user I/O pins if they are not used as memory interface
signals.
Table 8–1
Cyclone III device only.
Package
EQFP(1)
(1)
(1)
(1)
(1)
(1)
lists the number of DQS or DQ groups supported on each side of the
Left
Right
Top
Bottom (3),
Left
Right
Top
Bottom (3),
Left (4),
Right (4),
Top
Bottom
Left
Right
Top
Bottom (3),
Left
Right
Top
Bottom (3),
Left (4),
Right (4),
Top
Bottom
(2)
(2)
(2)
(2)
Side
(5)
(5)
(6)
(6)
(4)
(4)
(4)
(4)
Number
Groups
×8
0
0
1
1
0
0
1
1
1
1
2
2
0
0
1
1
0
0
1
1
1
1
2
2
Number
Groups
×9
0
0
0
0
0
0
0
0
1
1
2
2
0
0
0
0
0
0
0
0
1
1
2
2
Number
Groups
×16
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
Cyclone III Device Handbook, Volume 1
Number
Groups
×18
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
Number
Groups
×32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Number
Groups
×36
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8–3