EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 140

• Manufacturer Part Number: EP3C40F484C8N
• Description: IC CYCLONE III FPGA 40K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 331
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2475
• Family Type: Cyclone III
• No. Of I/o's: 331
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2492

7–16
High-Speed I/O Timing
Table 7–5. High-Speed I/O Timing Definitions
Figure 7–15. High-Speed I/O Timing Diagram
Cyclone III Device Handbook, Volume 1
Transmitter channel-to-channel skew
Sampling window
Receiver input skew margin
Input jitter tolerance (peak-to-peak)
Output jitter (peak-to-peak)
Note to
(1) The TCCS specification applies to the entire bank of differential I/O as long as the SERDES logic is placed in the logic array block (LAB) adjacent
to the output pins.
Table
7–5:
Parameter
This section discusses the timing budget, waveforms, and specifications for
source-synchronous signaling in the Cyclone III device family. Timing for
source-synchronous signaling is based on skew between the data and clock signals.
High-speed differential data transmission requires timing parameters provided by IC
vendors and requires you to consider the board skew, cable skew, and clock jitter. This
section provides information about high-speed I/O standards timing parameters in
the Cyclone III device family.
Table 7–5
Internal Clock
Input Clock
Input Data
Receiver
External
lists the parameters of the timing diagram as shown in
(1)
TCCS
TCCS
SW
RSKM
Symbol
—
—
RSKM
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
The timing difference between the fastest and slowest output
edges, including t
included in the TCCS measurement.
The period of time during which the data must be valid in order
for you to capture it correctly. The setup and hold times
determine the ideal strobe position in the sampling window.
T
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS. The RSKM equation is:
Allowed input jitter on the input clock to the PLL that is tolerable
while maintaining PLL lock.
Peak-to-peak output jitter from the PLL.
RSKM
SW
Sampling Window (SW)
Time Unit Interval (TUI)
= T
SU
=
+ T
(
--------------------------------------------- -
TUI SW TCCS
hd
+ PLL jitter.
–
CO
2
variation and clock skew. The clock is
–
RSKM
Description
)
TCCS
© December 2009 Altera Corporation
Figure
High-Speed I/O Timing
7–15.