EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 223

• Manufacturer Part Number: EP3C40F484C8N
• Description: IC CYCLONE III FPGA 40K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 331
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2475
• Family Type: Cyclone III
• No. Of I/o's: 331
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2492

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Table 9–19. JTAG CONFIG_IO (without JTAG_PROGRAM) Instruction Flows
© December 2009
ACTIVE_ENGAGE
PULSE_NCONFIG
Pulse nCONFIG pin
JTAG TAP Reset
Notes to
(1) “R” indicates that the instruction is to be executed before the next instruction, “O” indicates the optional instruction, “A” indicates that the
(2) Required if you use ACTIVE_DISENGAGE.
(3) Neither of the instruction is required if you use ACTIVE_ENGAGE.
(4) AP configuration is for Cyclone III devices only.
instruction must be executed, and “NA” indicates that the instruction is not allowed in this mode.
Table
JTAG Instruction
9–19:
1
Altera Corporation
The CONFIG_IO instruction does not hold the nSTATUS pin low until
reconfiguration. You must disengage the active configuration controllers (AS and AP)
by issuing the ACTIVE_DISENGAGE and ACTIVE_ENGAGE instructions when the
active configuration is interrupted. You must issue the ACTIVE_DISENGAGE
instruction alone or prior to the CONFIG_IO instruction if the JTAG_PROGRAM
instruction is to be issued later
controllers into the idle state. The active configuration controller is re-engaged after
user mode is reached using JTAG programming
While executing the CONFIG_IO instruction, all user I/Os are tri-stated.
If reconfiguration after interruption is performed using configuration modes (rather
than using JTAG_PROGRAM), it is not necessary to issue the ACTIVE_DISENGAGE
instruction prior to CONFIG_IO. You can start reconfiguration by either pulling the
nCONFIG pin low for at least 500 ns, or issuing the PULSE_NCONFIG instruction. If the
ACTIVE_DISENGAGE instruction was issued and the JTAG_PROGRAM instruction fails
to enter user mode, you must issue the ACTIVE_ENGAGE instruction to reactivate the
active configuration controller. Issuing the ACTIVE_ENGAGE instruction also triggers
the reconfiguration in configuration modes; therefore, it is not necessary to pull the
nCONFIG pin low or issue the PULSE_NCONFIG instruction.
PS
R
A
Configuration Scheme and Current State of the Cyclone III Device Family
Prior to User Mode
Configuration)
(Interrupting
FPP
A
R
R
A
A
(Table
AS
R
(3)
(3)
(2)
R
A
A
AP
(4)
R
9–20). This puts the active configuration
(3)
(3)
(2)
PS
A
R
(Note 1)
(Table
User Mode
FPP
A
R
(Part 2 of 2)
9–20).
R
AS
Cyclone III Device Handbook, Volume 1
O
O
R
(2)
AP
(4)
(2)
R
O
R
O
PS
—
—
—
—
Power Up
FPP AS
—
—
—
—
—
—
—
—
9–63
AP
(4)
—
—
—
—