EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 212

• Manufacturer Part Number: EP3C40F484C8N
• Description: IC CYCLONE III FPGA 40K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 331
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2475
• Family Type: Cyclone III
• No. Of I/o's: 331
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2492

9–52
Cyclone III Device Handbook, Volume 1
1
Cyclone III device family has dedicated JTAG pins that function as JTAG pins. You
can perform JTAG testing on Cyclone III device family before, during, and after
configuration. Cyclone III device family supports the BYPASS, IDCODE, and SAMPLE
instructions during configuration without interrupting configuration. All other JTAG
instructions can only be issued by first interrupting configuration and
reprogramming I/O pins using the ACTIVE_DISENGAGE and CONFIG_IO
instructions.
The CONFIG_IO instruction allows I/O buffers to be configured using the JTAG port
and when issued after the ACTIVE_DISENGAGE instruction interrupts configuration.
This instruction allows you to perform board-level testing prior to configuring the
Cyclone III device family or waiting for a configuration device to complete
configuration. Prior to issuing the CONFIG_IO instruction, you must issue the
ACTIVE_DISENGAGE instruction. This is because in Cyclone III device family, the
CONFIG_IO instruction does not hold nSTATUS low until reconfiguration, so you
must disengage the active configuration mode controller when active configuration is
interrupted. The ACTIVE_DISENGAGE instruction places the active configuration
mode controllers in an idle state prior to JTAG programming. Additionally, the
ACTIVE_ENGAGE instruction allows you to re-engage a disengaged active
configuration mode controller.
You must follow a specific flow when executing the CONFIG_IO,
ACTIVE_DISENGAGE, and ACTIVE_ENGAGE JTAG instructions in Cyclone III device
family. For more information about the instruction flow, refer to
on page
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on
Cyclone III device family do not affect JTAG boundary-scan or programming
operations. Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration, consider the dedicated configuration
pins.
Table 9–16
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–61.
lists how these pins must be connected during JTAG configuration.
© December 2009 Altera Corporation
“JTAG Instructions”
Configuration Features