EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 261

• Manufacturer Part Number: EP3C40F484C8N
• Description: IC CYCLONE III FPGA 40K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 331
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2475
• Family Type: Cyclone III
• No. Of I/o's: 331
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2492

Chapter 11: SEU Mitigation in the Cyclone III Device Family
Software Support
Accessing Error Detection Block Through User Logic
© December 2009
1
Altera Corporation
Figure 11–2. Enabling the Error Detection CRC Feature in the Quartus II Software
For Cyclone III LS devices, the “Enable Open Drain on CRC Error Pin” option is not
available because the Quartus II software sets the CRC_ERROR pin for the
Cyclone III LS device as open drain output by default.
The error detection circuit stores the computed 32-bit CRC signature in a 32-bit
register. This signature is read out by user logic from the core. The
<device>_crcblock primitive is a WYSIWYG component used to establish the
interface from user logic to the error detection circuit. The <device>_crcblock
primitive atom contains the input and output ports that must be included in the atom.
To access the logic array, the <device>_crcblock WYSIWYG atom must be
inserted into your design.
Cyclone III Device Handbook, Volume 1
11–7